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iig.htm
Enumerations
IigList
Instruction handlers
AAA AAD AAM AAS ADC ADCB ADCD ADCQ ADCW ADD ADDB ADDD ADDQ ADDW AND ANDB ANDD ANDQ ANDW BOUND BSF BSR BSWAP BT BTC BTCD BTCQ BTCW BTD BTQ BTR BTRD BTRQ BTRW BTS BTSD BTSQ BTSW BTW CALL CALLF CALLN CBW CDQ CDQE CLC CLD CLI CMC CMOVA CMOVAE CMOVB CMOVBE CMOVC CMOVE CMOVG CMOVGE CMOVL CMOVLE CMOVNA CMOVNAE CMOVNB CMOVNBE CMOVNC CMOVNE CMOVNG CMOVNGE CMOVNL CMOVNLE CMOVNO CMOVNP CMOVNS CMOVNZ CMOVO CMOVP CMOVPE CMOVPO CMOVS CMOVZ CMP CMPB CMPD CMPQ CMPS CMPSB CMPSD CMPSQ CMPSW CMPW CMPXCHG CMPXCHG16B CMPXCHG486 CMPXCHG8B CPUID CQO CWD CWDE DAA DAS DEC DECB DECD DECQ DECW DIV DIVB DIVD DIVQ DIVW ENTER ENTERD ENTERQ ENTERW HLT ICEBP IDIV IDIVB IDIVD IDIVQ IDIVW IMUL IMULB IMULD IMULQ IMULW IN INC INCB INCD INCQ INCW INS INSB INSD INSW INT INT1 INT3 INTO IRET IRETD IRETQ IRETW JA JAE JB JBE JC JCXZ JE JECXZ JG JGE JL JLE JMP JMPF JMPN JMPS JNA JNAE JNB JNBE JNC JNE JNG JNGE JNL JNLE JNO JNP JNS JNZ JO JP JPE JPO JRCXZ JS JZ LAHF LDS LEA LEAVE LEAVED LEAVEQ LEAVEW LES LFS LGS LODS LODSB LODSD LODSQ LODSW LOOP LOOPE LOOPNE LOOPNZ LOOPZ LSS LZCNT MOV MOVB MOVD MOVQ MOVS MOVSB MOVSD MOVSQ MOVSW MOVSX MOVSXB MOVSXD MOVSXW MOVW MOVZX MOVZXB MOVZXD MOVZXW MUL MULB MULD MULQ MULW NEG NEGB NEGD NEGQ NEGW NOT NOTB NOTD NOTQ NOTW OR ORB ORD ORQ ORW OUT OUTS OUTSB OUTSD OUTSW POP POPA POPAD POPAW POPCNT POPD POPF POPFD POPFQ POPFW POPQ POPW PSRAQ PUSH PUSHA PUSHAD PUSHAW PUSHD PUSHF PUSHFD PUSHFQ PUSHFW PUSHQ PUSHW RCL RCLB RCLD RCLQ RCLW RCR RCRB RCRD RCRQ RCRW RET RETF RETN ROL ROLB ROLD ROLQ ROLW ROR RORB RORD RORQ RORW SAHF SAL SAL2 SAL2B SAL2D SAL2Q SAL2W SALB SALC SALD SALQ SALW SAR SARB SARD SARQ SARW SBB SBBB SBBD SBBQ SBBW SCAS SCASB SCASD SCASQ SCASW SETA SETAE SETALC SETB SETBE SETC SETE SETG SETGE SETL SETLE SETNA SETNAE SETNB SETNBE SETNC SETNE SETNG SETNGE SETNL SETNLE SETNO SETNP SETNS SETNZ SETO SETP SETPE SETPO SETS SETZ SHL SHLB SHLD SHLQ SHLW SHR SHRB SHRD SHRQ SHRW SMI STC STD STI STOS STOSB STOSD STOSQ STOSW SUB SUBB SUBD SUBQ SUBW TEST TEST2 TEST2B TEST2D TEST2Q TEST2W TESTB TESTD TESTQ TESTW TZCNT UMOV XADD XCHG XLAT XLATB XOR XORB XORD XORQ XORW

IigHandlers
assemble general machine instructions.
See also
IiHandlers, [IntelVol2].
iig PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32,MAXPASSES=32
 INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.

iig HEAD  ; Start of module interface.
↑ %IigList
enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IigList requires the corresponding handler in this file.
See also
DictLookupIi
%IigList %SET \
MOV, \
CALL, \
RET, \
POP, \
POPAD, \
PUSH, \
PUSHAD, \
INC, \
DEC, \
CMP, \
TEST, \
ADD, \
SUB, \
AND, \
OR, \
XOR, \
STC, \
CLC, \
LEA, \
LOOP, \
JA, \
JAE, \
JB, \
JBE, \
JC, \
JCXZ, \
JE, \
JECXZ, \
JG, \
JGE, \
JL, \
JLE, \
JMP, \
JMPF, \
JMPN, \
JMPS, \
JNA, \
JNAE, \
JNB, \
JNBE, \
JNC, \
JNE, \
JNG, \
JNGE, \
JNL, \
JNLE, \
JNO, \
JNP, \
JNS, \
JNZ, \
JO, \
JP, \
JPE, \
JPO, \
JRCXZ, \
JS, \
JZ, \
AAA, \
AAD, \
AAM, \
AAS, \
ADC, \
ADCB, \
ADCD, \
ADCQ, \
ADCW, \
ADDB, \
ADDD, \
ADDQ, \
ADDW, \
ANDB, \
ANDD, \
ANDQ, \
ANDW, \
BOUND, \
BSF, \
BSR, \
BSWAP, \
BT, \
BTC, \
BTR, \
BTS, \
CALLF, \
CALLN, \
CBW, \
CDQ, \
CDQE, \
CLD, \
CLI, \
CMC, \
CMOVA, \
CMOVAE, \
CMOVB, \
CMOVBE, \
CMOVC, \
CMOVE, \
CMOVG, \
CMOVGE, \
CMOVL, \
CMOVLE, \
CMOVNA, \
CMOVNAE, \
CMOVNB, \
CMOVNBE, \
CMOVNC, \
CMOVNE, \
CMOVNG, \
CMOVNGE, \
CMOVNL, \
CMOVNLE, \
CMOVNO, \
CMOVNP, \
CMOVNS, \
CMOVNZ, \
CMOVO, \
CMOVP, \
CMOVPE, \
CMOVPO, \
CMOVS, \
CMOVZ, \
CMPB, \
CMPD, \
CMPQ, \
CMPS, \
CMPSB, \
CMPSD, \
CMPSQ, \
CMPSW, \
CMPW, \
CMPXCHG, \
CMPXCHG16B, \
CMPXCHG8B, \
CPUID, \
CQO, \
CWD, \
CWDE, \
DAA, \
DAS, \
DECB, \
DECD, \
DECQ, \
DECW, \
DIV, \
DIVB, \
DIVD, \
DIVQ, \
DIVW, \
HLT, \
ICEBP, \
IDIV, \
IDIVB, \
IDIVD, \
IDIVQ, \
IDIVW, \
IMUL, \
IMULB, \
IMULD, \
IMULQ, \
IMULW, \
IN, \
INCB, \
INCD, \
INCQ, \
INCW, \
INS, \
INSB, \
INSD, \
INSW, \
INT, \
INT1, \
INT3, \
INTO, \
IRET, \
IRETD, \
IRETQ, \
IRETW, \
LAHF, \
LDS, \
LES, \
LFS, \
LGS, \
LODS, \
LODSB, \
LODSD, \
LODSQ, \
LODSW, \
LOOPE, \
LOOPNE, \
LOOPNZ, \
LOOPZ, \
LSS, \
LZCNT, \
MOVB, \
MOVD, \
MOVQ, \
MOVS, \
MOVSB, \
MOVSD, \
MOVSQ, \
MOVSW, \
MOVSX, \
MOVSXB, \
MOVSXD, \
MOVSXW, \
MOVW, \
MOVZX, \
MOVZXB, \
MOVZXW, \
MUL, \
MULB, \
MULD, \
MULQ, \
MULW, \
NEG, \
NEGB, \
NEGD, \
NEGQ, \
NEGW, \
NOT, \
NOTB, \
NOTD, \
NOTQ, \
NOTW, \
ORB, \
ORD, \
ORQ, \
ORW, \
OUT, \
OUTS, \
OUTSB, \
OUTSD, \
OUTSW, \
POPA, \
POPAW, \
POPCNT, \
POPD, \
POPF, \
POPFD, \
POPFQ, \
POPFW, \
POPQ, \ 
POPW, \
PSRAQ, \
PUSHA, \
PUSHAW, \
PUSHD, \
PUSHF, \
PUSHFD, \
PUSHFQ, \
PUSHFW, \
PUSHQ, \
PUSHW, \
RCL, \
RCLB, \
RCLD, \
RCLQ, \
RCLW, \
RCR, \
RCRB, \
RCRD, \
RCRQ, \
RCRW, \
RETF, \
RETN, \
ROL, \
ROLB, \
ROLD, \
ROLQ, \
ROLW, \
ROR, \
RORB, \
RORD, \
RORQ, \
RORW, \
SAHF, \
SAL, \
SAL2, \
SAL2B, \
SAL2D, \
SAL2Q, \
SAL2W, \
SALB, \
SALC, \
SALD, \
SALQ, \
SALW, \
SAR, \
SARB, \
SARD, \
SARQ, \
SARW, \
SBB, \
SBBB, \
SBBD, \
SBBQ, \
SBBW, \
SCAS, \
SCASB, \
SCASD, \
SCASQ, \
SCASW, \
SETA, \
SETAE, \
SETALC, \
SETB, \
SETBE, \
SETC, \
SETE, \
SETG, \
SETGE, \
SETL, \
SETLE, \
SETNA, \
SETNAE, \
SETNB, \
SETNBE, \
SETNC, \
SETNE, \
SETNG, \
SETNGE, \
SETNL, \
SETNLE, \
SETNO, \
SETNP, \
SETNS, \
SETNZ, \
SETO, \
SETP, \
SETPE, \
SETPO, \
SETS, \
SETZ, \
SHL, \
SHLB, \
SHLD, \
SHLQ, \
SHLW, \
SHR, \
SHRB, \
SHRD, \
SHRQ, \
SHRW, \
STD, \
STI, \
STOS, \
STOSB, \
STOSD, \
STOSQ, \
STOSW, \
SUBB, \
SUBD, \
SUBQ, \
SUBW, \
TEST2, \
TEST2B, \
TEST2D, \
TEST2Q, \
TEST2W, \
TESTB, \
TESTD, \
TESTQ, \
TESTW, \
XADD, \
XCHG, \
XLAT, \
XLATB, \
XORB, \
XORD, \
XORQ, \
XORW, \
ENTER, \
ENTERW, \
ENTERD, \
ENTERQ, \
LEAVE, \
LEAVEW, \
LEAVED, \
LEAVEQ, \
TZCNT, \
CMPXCHG486, \
UMOV, \
SMI, \
MOVZXD, \
BTW, \
BTD, \
BTQ, \
BTCW, \
BTCD, \
BTCQ, \
BTSW, \
BTSD, \
BTSQ, \
BTRW, \
BTRD, \
BTRQ, \

;
  ENDHEAD iig  ; End of module interface.
↑ ADD
Add
Description
ADD
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x00 ^dw /r | 0x01 ^dW /r | 0x02 ^Dw /r | 0x03 ^DW /r | 0x04 ^w | 0x05 ^W | 0x80 ^w /0 | 0x81 ^W /0 | 0x83 ^SW /0
Flags
modified:O..SZAPC, defined:O..SZAPC
Tested by
t3100 t3110 t3120 t3230
IigADD:: PROC
    MOV CL,0 ; 0..7 specifies operation ADD, OR, ADC, SBB, AND, SUB, XOR, CMP.
.dg:IiAllowModifier CODE
    IiDataSize
    CMP DL,imm
    JNE .po:
    IiImmSize Operand2 ; Set II.MfgImplicitSize when %2 is immediate.
    CMPD [EDI+II.Operand2+EXP.Seg],0
    JZ .po:
    JSt [EDI+II.Operand2+EXP.Status],expPara,.sg:
    IiReloc iiRelocImmAbs
    JMP .po:
.sg:IiReloc iiRelocPara
.po:SHL ECX,3
    MOV AL,CL  ; Prepare opcode for accumulator version.
    SHL ECX,25 ; Position of /digit in iiPpgModDigit.
    OR ECX,iiPpgModRMd ; Prepare argument for IiModRM.
    IiDispatchFormat r8.r8,  r16.r16, r32.r32, r64.r64, \
                     m8.r8,  m16.r16, m32.r32, m64.r64, \
                     r8.m8,  r16.m16, r32.m32, r64.m64, \
                     r8.imm, r16.imm, r32.imm, r64.imm, \
                     m8.imm, m16.imm, m32.imm, m64.imm
.m8.imm:
    IiEncoding CODE=LONG, IMM=BYTE
    IiEmitOpcode 0x80
    IiOpEn M
    IiModRM ECX
    RET
.r8.imm:
    IiDispatchNotAccum Operand1, .m8.imm:
    IiDispatchCode LONG=.m8.imm:
    IiEncoding CODE=SHORT, IMM=BYTE ; Operand1 is AL, use short code.
    OR AL,0x04
    IiEmitOpcode EAX
    RET
.rm.imm8:
    IiEncoding CODE=LONG, IMM=BYTE
    IiEmitOpcode 0x83
    IiOpEn M
    IiModRM ECX ; /digit
    RET
.m16.imm:
    IiDispatchImm WORD=.rm.imm16: ; Explicitly requested IMM=WORD.
    CMPB [EDI+II.Operand2+EXP.Status],'N'
    JNE .rm.imm16:
    IiDispatchImmSize BYTE=.rm.imm8: ; Immediate fits to a byte.
.rm.imm16:
    IiEncoding CODE=LONG, IMM=WORD
    IiEmitOpcode 0x81
    IiOpEn M
    IiModRM ECX ; /digit
    RET
.EAX.imm8: ; Unless explicitly requested CODE=SHORT or IMM=DWORD, for ADD EAX,imm8 prefer
           ; long-opcode encoding 83 /0 ib which is two bytes shorter than short-opcode 05 id.
    IiDispatchCode SHORT=.EAX.imm32:
.m64.imm:
.m32.imm:
    IiDispatchImm DWORD=.rm.imm32: ; Explicitly requested IMM=DWORD.
    CMPB [EDI+II.Operand2+EXP.Status],'N'
    JNE .rm.imm32:
    IiDispatchImmSize BYTE=.rm.imm8: ; Immediate fits to a byte.
.rm.imm32:
    IiEncoding CODE=LONG, IMM=DWORD
    IiEmitOpcode 0x81
    IiOpEn M
    IiModRM ECX ; /digit
    RET
.r16.imm:
    IiDispatchNotAccum Operand1, .m16.imm:
    IiDispatchCode LONG=.m16.imm:
    IiEncoding CODE=SHORT, IMM=WORD ; Operand1 is AX, use short code.
    OR AL,0x05
    IiEmitOpcode EAX
    RET
.r64.imm:
.r32.imm:
    IiDispatchNotAccum Operand1, .m32.imm:
    CMPB [EDI+II.Operand2+EXP.Status],'N'
    JNE .EAX.imm32:
    IiDispatchImmSize BYTE=.EAX.imm8:
.EAX.imm32:
    IiEncoding CODE=SHORT, IMM=DWORD ; Operand1 is EAX or RAX, use short code.
    OR AL,0x05
    IiEmitOpcode EAX
    RET
.r8.m8:
    OR AL,0x02
    IiEncoding CODE=LONG
    IiEmitOpcode EAX
    IiOpEn RM
    IiModRM /r
    RET
.r8.r8:
    IiDispatchCode LONG=.r8.m8:
.m8.r8:
    IiEncoding CODE=SHORT
   ; OR AL,0x00
    IiEmitOpcode EAX
    IiOpEn MR
    IiModRM /r
    RET
.r16.m16:
.r32.m32:
.r64.m64:
    OR AL,0x03
    JMP .r8.m8:
.r16.r16:
.r32.r32:
.r64.r64:
    IiDispatchCode LONG=.r16.m16:
.m16.r16:
.m32.r32:
.m64.r64:
    OR AL,0x01
    JMP .m8.r8:
 ENDP IigADD::
↑ ADDB
Add BYTE
Tested by
t3100 t3110 t3120
IigADDB:: PROC
    IiSuffixed ADD,B
 ENDP IigADDB::
↑ ADDW
Add WORD
Tested by
t3100 t3110 t3120
IigADDW:: PROC
    IiSuffixed ADD,W
 ENDP IigADDW::
↑ ADDD
Add DWORD
Tested by
t3100 t3110 t3120
IigADDD:: PROC
    IiSuffixed ADD,D
 ENDP IigADDD::
↑ ADDQ
Add QWORD
Tested by
t3100 t3120
IigADDQ:: PROC
    IiSuffixed ADD,Q
 ENDP IigADDQ::
↑ OR
Logical Inclusive OR
Description
OR
Category
gen,logical
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x08 ^dw /r | 0x09 ^dW /r | 0x0A ^Dw /r | 0x0B ^DW /r | 0x0C ^w | 0x0D ^W | 0x80 ^w /1 | 0x81 ^W /1 | 0x83 ^SW /1
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:.....A.., values:O......C
Tested by
t3101 t3111 t3121 t3230
IigOR:: PROC
    MOV CL,1
    JMP IigADD.dg:
 ENDP IigOR::
↑ ORB
Or BYTE
Tested by
t3101 t3111 t3121
IigORB:: PROC
    IiSuffixed OR,B
 ENDP IigORB::
↑ ORW
Or WORD
Tested by
t3101 t3111 t3121
IigORW:: PROC
    IiSuffixed OR,W
 ENDP IigORW::
↑ ORD
Or DWORD
Tested by
t3101 t3111 t3121
IigORD:: PROC
    IiSuffixed OR,D
 ENDP IigORD::
↑ ORQ
Or QWORD
Tested by
t3101 t3121
IigORQ:: PROC
    IiSuffixed OR,Q
 ENDP IigORQ::
↑ ADC
Add with Carry
Description
ADC
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x10 ^dw /r | 0x11 ^dW /r | 0x12 ^Dw /r | 0x13 ^DW /r | 0x14 ^w | 0x15 ^W | 0x80 ^w /2 | 0x81 ^W /2 | 0x83 ^SW /2
Flags
tested:.......C, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3102 t3112 t3122 t3230
IigADC:: PROC
    MOV CL,2
    JMP IigADD.dg:
 ENDP IigADC::
↑ ADCB
Add with Carry BYTE
Tested by
t3102 t3112 t3122
IigADCB:: PROC
    IiSuffixed ADC,B
 ENDP IigADCB::
↑ ADCW
Add with Carry WORD
Tested by
t3102 t3112 t3122
IigADCW:: PROC
    IiSuffixed ADC,W
 ENDP IigADCW::
↑ ADCD
Add with Carry DWORD
Tested by
t3102 t3112 t3122
IigADCD:: PROC
    IiSuffixed ADC,D
 ENDP IigADCD::
↑ ADCQ
Add with Carry QWORD
Tested by
t3102 t3122
IigADCQ:: PROC
    IiSuffixed ADC,Q
 ENDP IigADCQ::
↑ SBB
Integer Subtraction with Borrow
Description
SBB
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x18 ^dw /r | 0x19 ^dW /r | 0x1A ^Dw /r | 0x1B ^DW /r | 0x1C ^w | 0x1D ^W | 0x80 ^w /3 | 0x81 ^W /3 | 0x83 ^SW /3
Flags
tested:.......C, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3103 t3113 t3123 t3230
IigSBB:: PROC
    MOV CL,3
    JMP IigADD.dg:
 ENDP IigSBB::
↑ SBBB
Subtract with Borrow BYTE
Tested by
t3103 t3113 t3123
IigSBBB:: PROC
    IiSuffixed SBB,B
 ENDP IigSBBB::
↑ SBBW
Subtract with Borrow WORD
Tested by
t3103 t3113 t3123
IigSBBW:: PROC
    IiSuffixed SBB,W
 ENDP IigSBBW::
↑ SBBD
Subtract with Borrow DWORD
Tested by
t3103 t3113 t3123
IigSBBD:: PROC
    IiSuffixed SBB,D
 ENDP IigSBBD::
↑ SBBQ
Subtract with Borrow QWORD
Tested by
t3103 t3123
IigSBBQ:: PROC
    IiSuffixed SBB,Q
 ENDP IigSBBQ::
↑ AND
Logical AND
Description
AND
Category
gen,logical
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x20 ^dw /r | 0x21 ^dW /r | 0x22 ^Dw /r | 0x23 ^DW /r | 0x24 ^w | 0x25 ^W | 0x80 ^w /4 | 0x81 ^W /4 | 0x83 ^SW /4
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:.....A.., values:O......C
Tested by
t3104 t3114 t3124 t3230
IigAND:: PROC
    MOV CL,4
    JMP IigADD.dg:
 ENDP IigAND::
↑ ANDB
And BYTE
Tested by
t3104 t3114 t3124
IigANDB:: PROC
    IiSuffixed AND,B
 ENDP IigANDB::
↑ ANDW
And WORD
Tested by
t3104 t3114 t3124
IigANDW:: PROC
    IiSuffixed AND,W
 ENDP IigANDW::
↑ ANDD
And DWORD
Tested by
t3104 t3114 t3124
IigANDD:: PROC
    IiSuffixed AND,D
 ENDP IigANDD::
↑ ANDQ
And QWORD
Tested by
t3104 t3124
IigANDQ:: PROC
    IiSuffixed AND,Q
 ENDP IigANDQ::
↑ SUB
Subtract
Description
SUB
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x28 ^dw /r | 0x29 ^dW /r | 0x2A ^Dw /r | 0x2B ^DW /r | 0x2C ^w | 0x2D ^W | 0x80 ^w /5 | 0x81 ^W /5 | 0x83 ^SW /5
Flags
modified:O..SZAPC, defined:O..SZAPC
Tested by
t3105 t3115 t3125 t3230
IigSUB:: PROC
    MOV CL,5
    JMP IigADD.dg:
 ENDP IigSUB::
↑ SUBB
Subtract BYTE
Tested by
t3105 t3115 t3125
IigSUBB:: PROC
    IiSuffixed SUB,B
 ENDP IigSUBB::
↑ SUBW
Subtract WORD
Tested by
t3105 t3115 t3125
IigSUBW:: PROC
    IiSuffixed SUB,W
 ENDP IigSUBW::
↑ SUBD
Subtract DWORD
Tested by
t3105 t3115 t3125
IigSUBD:: PROC
    IiSuffixed SUB,D
 ENDP IigSUBD::
↑ SUBQ
Subtract QWORD
Tested by
t3105 t3125
IigSUBQ:: PROC
    IiSuffixed SUB,Q
 ENDP IigSUBQ::
↑ XOR
Logical Exclusive OR
Description
XOR
Category
gen,logical
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x30 ^dw /r | 0x31 ^dW /r | 0x32 ^Dw /r | 0x33 ^DW /r | 0x34 ^w | 0x35 ^W | 0x80 ^w /6 | 0x81 ^W /6 | 0x83 ^SW /6
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:.....A.., values:O......C
Tested by
t3106 t3116 t3126 t3230
IigXOR:: PROC
    MOV CL,6
    JMP IigADD.dg:
 ENDP IigXOR::
↑ XORB
Exclusive Or BYTE
Tested by
t3106 t3116 t3126
IigXORB:: PROC
    IiSuffixed XOR,B
 ENDP IigXORB::
↑ XORW
Exclusive Or WORD
Tested by
t3106 t3116 t3126
IigXORW:: PROC
    IiSuffixed XOR,W
 ENDP IigXORW::
↑ XORD
Exclusive Or DWORD
Tested by
t3106 t3116 t3126
IigXORD:: PROC
    IiSuffixed XOR,D
 ENDP IigXORD::
↑ XORQ
Exclusive Or QWORD
Tested by
t3106 t3126
IigXORQ:: PROC
    IiSuffixed XOR,Q
 ENDP IigXORQ::
↑ CMP
Compare Two Operands
Description
CMP
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivds | Evqp,Ibs
Opcode
0x38 ^dw /r | 0x39 ^dW /r | 0x3A ^Dw /r | 0x3B ^DW /r | 0x3C ^w | 0x3D ^W | 0x80 ^w /7 | 0x81 ^W /7 | 0x83 ^SW /7
Flags
modified:O..SZAPC, defined:O..SZAPC
Tested by
t3107 t3117 t3127 t3230
IigCMP:: PROC
    MOV CL,7
    JMP IigADD.dg:
 ENDP IigCMP::
↑ CMPB
Compare BYTEs
Tested by
t3107 t3117 t3127
IigCMPB:: PROC
    IiSuffixed CMP,B
 ENDP IigCMPB::
↑ CMPW
Compare WORDs
Tested by
t3107 t3117 t3127
IigCMPW:: PROC
    IiSuffixed CMP,W
 ENDP IigCMPW::
↑ CMPD
Compare DWORDs
Tested by
t3107 t3117 t3127
IigCMPD:: PROC
    IiSuffixed CMP,D
 ENDP IigCMPD::
↑ CMPQ
Compare QWORDs
Tested by
t3107 t3127
IigCMPQ:: PROC
    IiSuffixed CMP,Q
 ENDP IigCMPQ::
↑ ROL
Rotate Left
Description
ROL
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /0 | 0xC1 ^W /0 | 0xD0 ^w /0 | 0xD1 ^W /0 | 0xD2 ^w /0 | 0xD3 ^W /0
Flags
modified:O..SZAPC, defined:O..SZAPC, undefined:O.......
CPU
01+
Tested by
t3050 t3060 t3070
IigROL:: PROC
    IiModRM /0
.rm:IiOpEn M
IiRequire 086
    IiAllowModifier CODE, IMM
    IiDataSize Operand1
    IiAssumeEmpty Operand2, 1
    MOV ECX,[EDI+II.Operand2+EXP.Low] ; Immediate value.
    DEC ECX ; ECX=0 if shift by 1, otherwise shift by CL or by imm8.
    IiDispatchFormat r8:, m8,  r8.imm,  m8.imm,  r8.r8,  m8.r8, \
                    r16, m16, r16.imm, m16.imm, r16.r8, m16.r8, \
                    r32, m32, r32.imm, m32.imm, r32.r8, m32.r8, \
                    r64, m64, r64.imm, m64.imm, r64.r8, m64.r8
.r8:
.m8:IiDispatchCode LONG=.C0:
    IiDispatchImm  BYTE=.C0:
    IiEncoding CODE=SHORT
    IiEmitOpcode 0xD0
    RET                    
.r8.imm:
.m8.imm:
    JECXZ .m8:
.C0:IiEmitOpcode 0xC0
    IiRequire 186
    IiEncoding CODE=LONG, IMM=BYTE
    IiEmitImm Operand2, BYTE
    RET
.r8.r8:
.m8.r8:
    IiAbortIfNot Operand2,CL
    IiEmitOpcode 0xD2
    RET
.r16:
.m16:
.r32:
.m32:
.r64:
.m64:IiDispatchCode LONG=.C1:
     IiDispatchImm  BYTE=.C1:
     IiEncoding CODE=SHORT
     IiEmitOpcode 0xD1
     RET
.r16.imm:
.m16.imm:
.r32.imm:
.m32.imm:
.r64.imm:
.m64.imm:
    JECXZ .m64:
.C1:IiEmitOpcode 0xC1
    IiRequire 186
    IiEncoding CODE=LONG, IMM=BYTE
    IiEmitImm Operand2, BYTE
    RET
.r16.r8:
.m16.r8:
.r32.r8:
.m32.r8:
.r64.r8:
.m64.r8:
    IiAbortIfNot Operand2,CL
    IiEmitOpcode 0xD3
    RET
 ENDP IigROL::
↑ ROLB
Rotate Left BYTE
Tested by
t3050 t3060 t3070
IigROLB:: PROC
    IiSuffixed ROL,B
 ENDP IigROLB::
↑ ROLW
Rotate Left WORD
Tested by
t3050 t3060 t3070
IigROLW:: PROC
    IiSuffixed ROL,W
 ENDP IigROLW::
↑ ROLD
Rotate Left DWORD
Tested by
t3050 t3060 t3070
IigROLD:: PROC
    IiSuffixed ROL,D
 ENDP IigROLD::
↑ ROLQ
Rotate Left QWORD
Tested by
t3070
IigROLQ:: PROC
    IiSuffixed ROL,Q
 ENDP IigROLQ::
↑ ROR
Rotate Right
Description
ROR
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /1 | 0xC1 ^W /1 | 0xD0 ^w /1 | 0xD1 ^W /1 | 0xD2 ^w /1 | 0xD3 ^W /1
Flags
modified:O..SZAPC, defined:O..SZAPC, undefined:O.......
CPU
01+
Tested by
t3051 t3061 t3071
IigROR:: PROC
    IiModRM /1
    JMP IigROL.rm:
 ENDP IigROR::
↑ RORB
Rotate Right BYTE
Tested by
t3051 t3061 t3071
IigRORB:: PROC
    IiSuffixed ROR,B
 ENDP IigRORB::
↑ RORW
Rotate Right WORD
Tested by
t3051 t3061 t3071
IigRORW:: PROC
    IiSuffixed ROR,W
 ENDP IigRORW::
↑ RORD
Rotate Right DWORD
Tested by
t3051 t3061 t3071
IigRORD:: PROC
    IiSuffixed ROR,D
 ENDP IigRORD::
↑ RORQ
Rotate Right QWORD
Tested by
t3071
IigRORQ:: PROC
    IiSuffixed ROR,Q
 ENDP IigRORQ::
↑ RCL
Rotate through Carry Left
Description
RCL
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /2 | 0xC1 ^W /2 | 0xD0 ^w /2 | 0xD1 ^W /2 | 0xD2 ^w /2 | 0xD3 ^W /2
Flags
tested:.......C, modified:O..SZAPC, defined:O..SZAPC, undefined:O.......
CPU
01+
Tested by
t3052 t3062 t3072
IigRCL:: PROC
    IiModRM /2
    JMP IigROL.rm:
 ENDP IigRCL::
↑ RCLB
Rotate through Carry Left BYTE
Tested by
t3052 t3062 t3072
IigRCLB:: PROC
    IiSuffixed RCL,B
 ENDP IigRCLB::
↑ RCLW
Rotate through Carry Left WORD
Tested by
t3052 t3062 t3072
IigRCLW:: PROC
    IiSuffixed RCL,W
 ENDP IigRCLW::
↑ RCLD
Rotate through Carry Left DWORD
Tested by
t3052 t3062 t3072
IigRCLD:: PROC
    IiSuffixed RCL,D
 ENDP IigRCLD::
↑ RCLQ
Rotate through Carry Left QWORD
Tested by
t3072
IigRCLQ:: PROC
    IiSuffixed RCL,Q
 ENDP IigRCLQ::
↑ RCR
Rotate through Carry Right
Description
RCR
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /3 | 0xC1 ^W /3 | 0xD0 ^w /3 | 0xD1 ^W /3 | 0xD2 ^w /3 | 0xD3 ^W /3
Flags
tested:.......C, modified:O..SZAPC, defined:O..SZAPC, undefined:O.......
CPU
01+
Tested by
t3053 t3063 t3073
IigRCR:: PROC
    IiModRM /3
    JMP IigROL.rm:
 ENDP IigRCR::
↑ RCRB
Rotate through Carry Right BYTE
Tested by
t3053 t3063 t3073
IigRCRB:: PROC
    IiSuffixed RCR,B
 ENDP IigRCRB::
↑ RCRW
Rotate throudh Carry Right WORD
Tested by
t3053 t3063 t3073
IigRCRW:: PROC
    IiSuffixed RCR,W
 ENDP IigRCRW::
↑ RCRD
Rotate through Carry Right DWORD
Tested by
t3053 t3063 t3073
IigRCRD:: PROC
    IiSuffixed RCR,D
 ENDP IigRCRD::
↑ RCRQ
Rotate through Carry Right QWORD
Tested by
t3073
IigRCRQ:: PROC
    IiSuffixed RCR,Q
 ENDP IigRCRQ::
↑ SHL
Shift logical Left
Description
SHL
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /4 | 0xC1 ^W /4 | 0xD0 ^w /4 | 0xD1 ^W /4 | 0xD2 ^w /4 | 0xD3 ^W /4
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A.C
CPU
01+
Tested by
t3054 t3064 t3074
IigSHL:: PROC
    IiModRM /4
    JMP IigROL.rm:
 ENDP IigSHL::
↑ SHLB
Shift logical Left BYTE
Tested by
t3054 t3064 t3074
IigSHLB:: PROC
    IiSuffixed SHL,B
 ENDP IigSHLB::
↑ SHLW
Shift logical Left WORD
Tested by
t3054 t3064 t3074
IigSHLW:: PROC
    IiSuffixed SHL,W
 ENDP IigSHLW::
↑ SHLD
Double Precision Shift Left or
Shift logical Left DWORD
Description
SHLD
Category
gen,shftrot
Operands
Evqp,Gvqp,Ib | Evqp,Gvqp,CL
Opcode
0x0FA4 ^d /r | 0x0FA5 ^d /r
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A.C
CPU
03+
Tested by
t3054 t3064 t3074 t3245
IigSHLD:: PROC
    IiDispatchSingleShift .Single:
    MOV AL,0xA4
.op:IiAllowModifier IMM
    IiRequire 386
    IiDataSize ; Operand2
    IiEmitOpcode 0x0F
    IiOpEn MR
    IiModRM /r 
    IiAssumeEmpty Operand3, 1
    IiDispatchFormat r16.r16, m16.r16, r16.r16.imm, m16.r16.imm, r16.r16.r8, m16.r16.r8, \
                     r32.r32, m32.r32, r32.r32.imm, m32.r32.imm, r32.r32.r8, m32.r32.r8, \
                     r64.r64, m64.r64, r64.r64.imm, m64.r64.imm, r64.r64.r8, m64.r64.r8
.Single: IiSuffixed SHL,D                     
.r16.r16.r8:
.m16.r16.r8:
.r32.r32.r8:
.m32.r32.r8:
.r64.r64.r8:
.m64.r64.r8:
    IiAbortIfNot Operand3, CL
    INC AL ; Change opcode 0xA4->0xA5, 0xAC->0xAD.
    IiEmitOpcode EAX
    RET 
.r16.r16:
.m16.r16:
.r32.r32:
.m32.r32:
.r64.r64:
.m64.r64:
.r16.r16.imm:
.m16.r16.imm:
.r32.r32.imm:
.m32.r32.imm:
.r64.r64.imm:
.m64.r64.imm:
    IiEmitOpcode EAX
    IiEmitImm Operand3, BYTE
    RET                      
 ENDP IigSHLD::
↑ SHLQ
Shift logical Left QWORD
Tested by
t3074
IigSHLQ:: PROC
    IiSuffixed SHL,Q
 ENDP IigSHLQ::
↑ SAL
Shift Arithmetic Left
Description
SAL
Comment
SAL is identical with SHL by definition. See also SAL2.
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /4 | 0xC1 ^W /4 | 0xD0 ^w /4 | 0xD1 ^W /4 | 0xD2 ^w /4 | 0xD3 ^W /4
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A.C
CPU
01+
Tested by
t3058 t3068 t3078
IigSAL:: PROC
    JMP IigSHL:
 ENDP IigSAL::
↑ SALB
Shift Arithmetic Left BYTE
Tested by
t3058 t3068 t3078
IigSALB:: PROC
    IiSuffixed SAL,B
 ENDP IigSALB::
↑ SALW
Shift Arithmetic Left WORD
Tested by
t3058 t3068 t3078
IigSALW:: PROC
    IiSuffixed SAL,W
 ENDP IigSALW::
↑ SALD
Shift Arithmetic Left DWORD
Tested by
t3058 t3068 t3078
IigSALD:: PROC
    IiSuffixed SAL,D
 ENDP IigSALD::
↑ SALQ
Shift Arithmetic Left QWORD
Tested by
t3078
IigSALQ:: PROC
    IiSuffixed SAL,Q
 ENDP IigSALQ::
↑ SHR
Shift logical Right
Description
SHR
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /5 | 0xC1 ^W /5 | 0xD0 ^w /5 | 0xD1 ^W /5 | 0xD2 ^w /5 | 0xD3 ^W /5
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A.C
CPU
01+
Tested by
t3055 t3065 t3075
IigSHR:: PROC
    IiModRM /5
    JMP IigROL.rm:
 ENDP IigSHR::
↑ SHRB
Shift logical Right BYTE
Tested by
t3055 t3065 t3075
IigSHRB:: PROC
    IiSuffixed SHR,B
 ENDP IigSHRB::
↑ SHRW
Shift logical Right WORD
Tested by
t3055 t3065 t3075
IigSHRW:: PROC
    IiSuffixed SHR,W
 ENDP IigSHRW::
↑ SHRD
Double Precision Shift Right or
Shift logical Right DWORD
Description
SHRD
Category
gen,shftrot
Operands
Evqp,Gvqp,Ib | Evqp,Gvqp,CL
Opcode
0x0FAC ^d /r | 0x0FAD ^d /r
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A.C
CPU
03+
Tested by
t3055 t3065 t3075 t3245
IigSHRD:: PROC
    IiDispatchSingleShift .Single:
    MOV AL,0xAC
    JMP IigSHLD.op:
.Single:IiSuffixed SHR,D    
 ENDP IigSHRD::
↑ SHRQ
Shift logical Right QWORD
Tested by
t3075
IigSHRQ:: PROC
    IiSuffixed SHR,Q
 ENDP IigSHRQ::
↑ SAL2
Shift Arithmetic Left undocumented alternate
Opcode
/6
See also
SAL.
Tested by
t3056 t3066 t3076
IigSAL2:: PROC
    IiRequire UNDOC
    IiModRM /6
    JMP IigROL.rm:
 ENDP IigSAL2::
↑ SAL2B
Shift Arithmetic Left undocumented alternate BYTE
Tested by
t3056 t3066 t3076
IigSAL2B:: PROC
    IiSuffixed SAL2,B
 ENDP IigSAL2B::
↑ SAL2W
Shift Arithmetic Left undocumented alternate WORD
Tested by
t3056 t3066 t3076
IigSAL2W:: PROC
    IiSuffixed SAL2,W
 ENDP IigSAL2W::
↑ SAL2D
Shift Arithmetic Left undocumented alternate DWORD
Tested by
t3056 t3066 t3076
IigSAL2D:: PROC
    IiSuffixed SAL2,D
 ENDP IigSAL2D::
↑ SAL2Q
Shift Arithmetic Left undocumented alternate QWORD
Tested by
t3076
IigSAL2Q:: PROC
    IiSuffixed SAL2,Q
 ENDP IigSAL2Q::
↑ SAR
Shift Arithmetic Right
Description
SAR
Category
gen,shftrot
Operands
Eb,Ib | Evqp,Ib | Eb,1 | Evqp,1 | Eb,CL | Evqp,CL
Opcode
0xC0 ^w /7 | 0xC1 ^W /7 | 0xD0 ^w /7 | 0xD1 ^W /7 | 0xD2 ^w /7 | 0xD3 ^W /7
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:O....A..
CPU
01+
Tested by
t3057 t3067 t3077
IigSAR:: PROC
    IiModRM /7
    JMP IigROL.rm:
 ENDP IigSAR::
↑ SARB
Shift Arithmetic Right BYTE
Tested by
t3057 t3067 t3077
IigSARB:: PROC
    IiSuffixed SAR,B
 ENDP IigSARB::
↑ SARW
Shift Arithmetic Right WORD
Tested by
t3057 t3067 t3077
IigSARW:: PROC
    IiSuffixed SAR,W
 ENDP IigSARW::
↑ SARD
Shift Arithmetic Right DWORD
Tested by
t3057 t3067 t3077
IigSARD:: PROC
    IiSuffixed SAR,D
 ENDP IigSARD::
↑ SARQ
Shift Arithmetic Right QWORD
Tested by
t3077
IigSARQ:: PROC
    IiSuffixed SAR,Q
 ENDP IigSARQ::
↑ NOT
One's Complement Negation
Description
NOT
Category
gen,logical
Operands
Eb | Evqp
Opcode
0xF6 ^w /2 | 0xF7 ^W /2
Tested by
t3251 t3252 t3253
IigNOT:: PROC
    IiModRM /2
.rm:IiOpEn M
    IiDataSize Operand1
    IiDispatchFormat  r8:,  m8, r16, m16, r32, m32, r64, m64
.r8:
.m8:IiEmitOpcode 0xF6
    RET
.r16:
.m16:
.r32:
.m32:
.r64:
.m64:IiEmitOpcode 0xF7
     RET
 ENDP IigNOT::
↑ NOTB
One's Complement Negation BYTE
Tested by
t3251 t3252 t3253
IigNOTB:: PROC
    IiSuffixed NOT,B
 ENDP IigNOTB::
↑ NOTW
One's Complement Negation WORD
Tested by
t3251 t3252 t3253
IigNOTW:: PROC
    IiSuffixed NOT,W
 ENDP IigNOTW::
↑ NOTD
One's Complement Negation DWORD
Tested by
t3251 t3252 t3253
IigNOTD:: PROC
    IiSuffixed NOT,D
 ENDP IigNOTD::
↑ NOTQ
One's Complement Negation QWORD
Tested by
t3253
IigNOTQ:: PROC
    IiSuffixed NOT,Q
 ENDP IigNOTQ::
↑ NEG
Two's Complement Negation
Description
NEG
Category
gen,arith,binary
Operands
Eb | Evqp
Opcode
0xF6 ^w /3 | 0xF7 ^W /3
Flags
modified:O..SZAPC, defined:O..SZAPC
Tested by
t3251 t3252 t3253
IigNEG:: PROC
    IiModRM /3
    JMP IigNOT.rm:
 ENDP IigNEG::
↑ NEGB
Two's Complement Negation BYTE
Tested by
t3251 t3252 t3253
IigNEGB:: PROC
    IiSuffixed NEG,B
 ENDP IigNEGB::
↑ NEGW
Two's Complement Negation WORD
Tested by
t3251 t3252 t3253
IigNEGW:: PROC
    IiSuffixed NEG,W
 ENDP IigNEGW::
↑ NEGD
Two's Complement Negation DWORD
Tested by
t3251 t3252 t3253
IigNEGD:: PROC
    IiSuffixed NEG,D
 ENDP IigNEGD::
↑ NEGQ
Two's Complement Negation QWORD
Tested by
t3253
IigNEGQ:: PROC
    IiSuffixed NEG,Q
 ENDP IigNEGQ::
↑ MUL
Unsigned Multiply
Description
MUL
Category
gen,arith,binary
Operands
AX,AL,Eb | rDX,rAX,Evqp
Opcode
0xF6 ^w /4 | 0xF7 ^W /4
Flags
modified:O..SZAPC, defined:O......C, undefined:...SZAP.
Tested by
t3251 t3252 t3253
IigMUL:: PROC
    IiModRM /4
    JMP IigNOT.rm:
 ENDP IigMUL::
↑ MULB
Unsigned Multiply by BYTE
Tested by
t3251 t3252 t3253
IigMULB:: PROC
    IiSuffixed MUL,B
 ENDP IigMULB::
↑ MULW
Unsigned Multiply by WORD
Tested by
t3251 t3252 t3253
IigMULW:: PROC
    IiSuffixed MUL,W
 ENDP IigMULW::
↑ MULD
Unsigned Multiply by DWORD
Tested by
t3251 t3252 t3253
IigMULD:: PROC
    IiSuffixed MUL,D
 ENDP IigMULD::
↑ MULQ
Unsigned Multiply by QWORD
Tested by
t3253 t3273
IigMULQ:: PROC
    IiSuffixed MUL,Q
 ENDP IigMULQ::
↑ DIV
Unsigned Divide
Description
DIV
Category
gen,arith,binary
Operands
AL,AH,AX,Eb | rDX,rAX,Evqp
Opcode
0xF6 ^w /6 | 0xF7 ^w /6
Flags
modified:O..SZAPC, undefined:O..SZAPC
Tested by
t3251 t3252 t3253
IigDIV:: PROC
    IiModRM /6
    JMP IigNOT.rm:
 ENDP IigDIV::
↑ DIVB
Unsigned Divide by BYTE
Tested by
t3251 t3252 t3253
IigDIVB:: PROC
    IiSuffixed DIV,B
 ENDP IigDIVB::
↑ DIVW
Unsigned Divide by WORD
Tested by
t3251 t3252 t3253
IigDIVW:: PROC
    IiSuffixed DIV,W
 ENDP IigDIVW::
↑ DIVD
Unsigned Divide by DWORD
Tested by
t3253
IigDIVD:: PROC
    IiSuffixed DIV,D
 ENDP IigDIVD::
↑ DIVQ
Unsigned Divide by QWORD
Tested by
t3251 t3252 t3253
IigDIVQ:: PROC
    IiSuffixed DIV,Q
 ENDP IigDIVQ::
↑ IDIV
Signed Divide
Description
IDIV
Category
gen,arith,binary
Operands
AL,AH,AX,Eb | rDX,rAX,Evqp
Opcode
0xF6 ^w /7 | 0xF7 ^w /7
Flags
modified:O..SZAPC, undefined:O..SZAPC
Tested by
t3251 t3252 t3253
IigIDIV:: PROC
    IiModRM /7
    JMP IigNOT.rm:
 ENDP IigIDIV::
↑ IDIVB
Signed Divide by BYTE
Tested by
t3251 t3252 t3253
IigIDIVB:: PROC
    IiSuffixed IDIV,B
 ENDP IigIDIVB::
↑ IDIVW
Signed Divide by WORD
Tested by
t3251 t3252 t3253
IigIDIVW:: PROC
    IiSuffixed IDIV,W
 ENDP IigIDIVW::
↑ IDIVD
Signed Divide by DWORD
Tested by
t3251 t3252 t3253
IigIDIVD:: PROC
    IiSuffixed IDIV,D
 ENDP IigIDIVD::
↑ IDIVQ
Signed Divide by QWORD
Tested by
t3253
IigIDIVQ:: PROC
    IiSuffixed IDIV,Q
 ENDP IigIDIVQ::
↑ TEST
Logical Compare
Description
TEST
Reference
TEST AL, imm8, CODE=SHORTA8 ib
TEST rAX, imm, CODE=SHORTA9 imm
TEST r/m8, imm8, CODE=LONGF6 /0 ib
TEST reg/mem, imm, CODE=LONGF7 /0 imm
TEST r/m8, r8, CODE=SHORT84 /r
TEST r8, r/m8, CODE=LONG84 /r
TEST reg/mem, reg, CODE=SHORT85 /r
TEST reg, reg/mem, CODE=LONG85 /r
Category
gen,arith,binary
Operands
Eb,Gb | Evqp,Gvqp | AL,Ib | rAX,Ivds | Eb,Ib | Evqp,Ivqp
Opcode
0x84 ^dw /r | 0x85 ^dW /r | 0xA8 ^w | 0xA9 ^W | 0xF6 ^w /0 | 0xF7 ^W /0
Flags
modified:O..SZAPC, defined:O..SZ.PC, undefined:.....A.., values:O......C
Tested by
t3261 t3262 t3263
IigTEST:: PROC
    IiAllowModifier CODE
    IiAssumeEmpty Operand2,Operand1
    IiOpEn M
    IiDataSize
    IiDispatchFormat r8:, r16, r32, r64, r8.imm, r8.r8, r8.m8, m8.imm, m8.r8, r16.imm, r16.r16, r16.m16, m16.imm, m16.r16, \
                   r32.imm, r32.r32, r32.m32, m32.imm, m32.r32, r64.imm, r64.r64, r64.m64, m64.imm, m64.r64
.r8.m8:
    IiEncoding CODE=LONG
    IiSwap Operand1,Operand2
    JMP .B:
.r8.r8:
.r8:IiDispatchCode LONG=.r8.m8:
.m8.r8:
    IiEncoding CODE=SHORT
 .B:IiEmitOpcode 0x84
    IiOpEn MR
    IiModRM /r
    RET
.r16.m16:
.r32.m32:
.r64.m64:
    IiEncoding CODE=LONG
    IiSwap Operand1,Operand2
    JMP .W:
.r16.r16:
.r32.r32:
.r64.r64:
.r16:
.r32:
.r64:IiDispatchCode LONG=.r16.m16:
.m16.r16:
.m32.r32:
.m64.r64:
     IiEncoding CODE=SHORT
 .W: IiEmitOpcode 0x85
     IiOpEn MR
     IiModRM /r
     RET
.r8.imm:
     IiDispatchNotAccum Operand1,.m8.imm:
     IiDispatchCode LONG=.m8.imm:
     IiEncoding CODE=SHORT
     IiEmitOpcode 0xA8
     IiEmitImm Operand2, BYTE
     RET
.m8.imm:
     IiEncoding CODE=LONG
     IiEmitOpcode 0xF6
     IiModRM /0
     IiEmitImm Operand2, BYTE
     RET
.r16.imm:
     IiDispatchNotAccum Operand1,.m16.imm:
     IiDispatchCode LONG=.m16.imm:
     IiEncoding CODE=SHORT
     IiEmitOpcode 0xA9
     IiEmitImm Operand2, WORD
     RET
.m16.imm:
     IiEncoding CODE=LONG
     IiEmitOpcode 0xF7
     IiModRM /0
     IiEmitImm Operand2, WORD
     RET
.r32.imm:
.r64.imm:
     IiDispatchNotAccum Operand1,.m32.imm:
     IiDispatchCode LONG=.m32.imm:
     IiEncoding CODE=SHORT
     IiEmitOpcode 0xA9
     IiEmitImm Operand2, DWORD
     RET
.m32.imm:
.m64.imm:
     IiEncoding CODE=LONG
     IiEmitOpcode 0xF7
     IiModRM /0
     IiEmitImm Operand2, DWORD
     RET
 ENDP IigTEST::
↑ TESTB
Logical Compare BYTEs
Tested by
t3261 t3262 t3263
IigTESTB:: PROC
    IiSuffixed TEST,B
 ENDP IigTESTB::
↑ TESTW
Logical Compare WORDs
Tested by
t3261 t3262 t3263
IigTESTW:: PROC
    IiSuffixed TEST,W
 ENDP IigTESTW::
↑ TESTD
Logical Compare DWORDs
Tested by
t3261 t3262 t3263
IigTESTD:: PROC
    IiSuffixed TEST,D
 ENDP IigTESTD::
↑ TESTQ
Logical Compare QWORD
Tested by
t3263
IigTESTQ:: PROC
    IiSuffixed TEST,Q
 ENDP IigTESTQ::
↑ TEST2
Logical Compare alternate
Comment
Same encoding as TEST except for F6 /0 imm encoded as F6 /1 imm and instead of F7 /0 imm is encoded as F7 /1 imm.
Opcode
0xF6 /1 | 0xF7 /1
Tested by
t3261 t3262 t3263
IigTEST2:: PROC
    IiRequire UNDOC
    ORD [EDI+II.Ppg],0x1000_0000 ; Change /digit from /0 to /1.
    JMP IigTEST
 ENDP IigTEST2::
↑ TEST2B
Logical Compare alternate BYTEs
Tested by
t3261 t3262 t3263
IigTEST2B:: PROC
    IiSuffixed TEST2,B
 ENDP IigTEST2B::
↑ TEST2W
Logical Compare alternate WORDs
Tested by
t3261 t3262 t3263
IigTEST2W:: PROC
    IiSuffixed TEST2,W
 ENDP IigTEST2W::
↑ TEST2D
Logical Compare alternate DWORDs
Tested by
t3261 t3262 t3263
IigTEST2D:: PROC
    IiSuffixed TEST2,D
 ENDP IigTEST2D::
↑ TEST2Q
Logical Compare alternate QWORDs
Tested by
t3263
IigTEST2Q:: PROC
    IiSuffixed TEST2,Q
 ENDP IigTEST2Q::
↑ IMUL
Signed Multiply
Description
IMUL
Category
gen,arith,binary
Operands
Gvqp,Evqp,Ivds | Gvqp,Evqp,Ibs | AX,AL,Eb | rDX,rAX,Evqp | Gvqp,Evqp
Opcode
0x69 /r | 0x6B ^S /r | 0xF6 ^w /5 | 0xF7 ^w /5 | 0x0FAF ^DW /r
Flags
modified:O..SZAPC, defined:O......C, undefined:...SZAP.
CPU
01+
Tested by
t3271 t3272 t3273
IigIMUL:: PROC
    IiDataSize Operand1
    IiDispatchFormat r8:, m8, r16, m16, r32, m32, r64, m64, \
    r16.r16, r16.m16, r32.r32, r32.m32, r64.r64, r64.m64, \
    r16.r16.imm, r16.m16.imm, r32.r32.imm, r32.m32.imm, r64.r64.imm, r64.m64.imm
.m8:
.r8: IiEmitOpcode 0xF6
     IiOpEn M
     IiModRM /5
     RET
.r16:
.r32:
.r64:
.m16:
.m32:
.m64:IiEmitOpcode 0xF7
     IiOpEn M
     IiModRM /5
     RET
.r16.r16:
.r16.m16:
.r32.r32:
.r32.m32:
.r64.r64:
.r64.m64:
     IiEmitOpcode 0x0F,0xAF
     IiOpEn RM
     IiModRM /r
     RET
.r16.r16.imm:
.r16.m16.imm:
.r32.r32.imm:
.r32.m32.imm:
.r64.r64.imm:
.r64.m64.imm:
     IiRequire 186
     IiOpEn RM
     IiModRM /r
     IiAllowModifier IMM
     IiImmSize Operand3
     IiDispatchImm WORD=.69:, DWORD=.69:
     JNSt [EDI+II.MfgImplicit],iiMfgIMM_BYTE,.69:
     IiEmitOpcode 0x6B
     IiEmitImm Operand3, BYTE
     RET
.69: IiEmitOpcode 0x69
     SHR EDX,16 ; Operand1 (r16/r32/r64) shift to DL.
     CMP DL,r16
     JE .W:
     IiEmitImm Operand3, DWORD
     RET
 .W: IiEmitImm Operand3, WORD
     RET
 ENDP IigIMUL::
↑ IMULB
Signed Multiply by BYTE
Tested by
t3271 t3272 t3273
IigIMULB:: PROC
    IiSuffixed IMUL,B
 ENDP IigIMULB::
↑ IMULW
Signed Multiply by WORD
Tested by
t3271 t3272 t3273
IigIMULW:: PROC
    IiSuffixed IMUL,W
 ENDP IigIMULW::
↑ IMULD
Signed Multiply by DWORD
Tested by
t3271 t3272 t3273
IigIMULD:: PROC
    IiSuffixed IMUL,D
 ENDP IigIMULD::
↑ IMULQ
Signed Multiply by QWORD
IigIMULQ:: PROC
    IiSuffixed IMUL,Q
 ENDP IigIMULQ::
↑ INC
Increment by 1
Description
INC
Category
gen,arith,binary
Operands
Zv | Eb | Evqp
Opcode
0x40 ^+r | 0xFE ^w /0 | 0xFF ^W /0
Flags
modified:O..SZAP., defined:O..SZAP.
Tested by
t3281 t3282 t3283 t3284
IigINC:: PROC
     IiModRM /0
     MOV CL,0x40
.rm: IiAllowModifier CODE
     IiAllowPrefix LOCK
     IiDataSize Operand1
     IiOpEn M
     IiDispatchFormat  r8:, m8, r16, m16, r32, m32, r64, m64
.r8:
.m8:IiEmitOpcode 0xFE
    RET
.m16:
.m32:
.r64:
.m64:
    IiEncoding CODE=LONG
    IiEmitOpcode 0xFF
    RET
.r16:
.r32:
    IiDispatchCode LONG=.m16:
    IiDispatchWidth BITS64=.m16:
    IiEncoding CODE=SHORT
    SetSt [EDI+II.Ppg],iiPpgMod01 ; Change ModRM byte 0xC0+r to opcode byte 0x40+r.
    RET
 ENDP IigINC::
↑ INCB
Increment BYTE
Tested by
t3281 t3282 t3283 t3284
IigINCB:: PROC
    IiSuffixed INC,B
 ENDP IigINCB::
↑ INCW
Increment WORD
Tested by
t3281 t3282 t3283 t3284
IigINCW:: PROC
    IiSuffixed INC,W
 ENDP IigINCW::
↑ INCD
Increment DWORD
Tested by
t3281 t3282 t3283 t3284
IigINCD:: PROC
    IiSuffixed INC,D
 ENDP IigINCD::
↑ INCQ
Increment QWORD
Tested by
t3283 t3284
IigINCQ:: PROC
    IiSuffixed INC,Q
 ENDP IigINCQ::
↑ DEC
Decrement by 1
Description
DEC
Category
gen,arith,binary
Operands
Zv | Eb | Evqp
Opcode
0x48 ^+r | 0xFE ^w /1 | 0xFF ^W /1
Flags
modified:O..SZAP., defined:O..SZAP.
Tested by
t3281 t3282 t3283 t3285
IigDEC:: PROC
    IiModRM /1
    JMP IigINC.rm:
 ENDP IigDEC::
↑ DECB
Decrement BYTE
Tested by
t3281 t3282 t3283 t3285
IigDECB:: PROC
    IiSuffixed DEC,B
 ENDP IigDECB::
↑ DECW
Decrement WORD
Tested by
t3281 t3282 t3283 t3285
IigDECW:: PROC
    IiSuffixed DEC,W
 ENDP IigDECW::
↑ DECD
Decrement DWORD
Tested by
t3281 t3282 t3283 t3285
IigDECD:: PROC
    IiSuffixed DEC,D
 ENDP IigDECD::
↑ DECQ
Decrement QWORD
Tested by
t3283 t3285
IigDECQ:: PROC
    IiSuffixed DEC,Q
 ENDP IigDECQ::
↑ PUSH
Push Word, Doubleword or Quadword Onto the Stack
Description
PUSH
Comment
This instruction uses nonstandard operand width, therefore it cannot use macro IiDataSize to investigate effective operand-size of immediate value. See also discussion here.
Category
gen,stack segreg
Operands
ES | CS | SS | DS | Zv | Zvq | Ivs | Ibss | Ev | Evq | FS | GS
Opcode
0x06 ^sr | 0x0E ^sR | 0x16 ^Sr | 0x1E ^SR | 0x50 ^+r | 0x50 ^+r | 0x68 | 0x6A ^S | 0xFF /6 | 0xFF /6 | 0x0FA0 ^Sre | 0x0FA8 ^SrE
Tested by
t3191 t3192
IigPUSH:: PROC
    IiDataSize Operand1, UseSegment=ON ; Unspecified opsize defaults to segment width.
    IiOpEn M
    IiDispatchFormat imm, r32, r64, r8:, r16, m32, m64, m16, m8, Sreg
.r8:
.m8: IiAbort '6753' ; 8bit register or memory operand cannot be pushed/popped.
.m32:IiAbortIf64
.m16:
.m64:IiEmitOpcode 0xFF
     IiModRM /6
     IiRemoveREXW
     RET
.reg:IiEncoding CODE=LONG     
     JMP .m16:
.r32:IiAbortIf64
.r16:
.r64:IiAllowModifier CODE
     IiDispatchCode LONG=.reg:
     IiEncoding CODE=SHORT
     IiModRM /2
     SetSt [EDI+II.Ppg],iiPpgMod01
     IiRemoveREXW
     RET
.immD: ; Operand-size = DWORD.
     IiAbortIf64
     IiDispatchImm DWORD=.id:   ; Explicitly requested immediate encoding IMM=DWORD.
     IiDispatchImmSize BYTE=.ib:; Immediate operand fits to a byte. 
.id: IiEmitOpcode 0x68
     IiEmitImm Operand1, DWORD
     RET
.ib: IiEmitOpcode 0x6A
     IiEmitImm Operand1, BYTE
     RET
.immW: ; Operand-size = WORD.
     IiDispatchImm WORD=.iw:    ; Explicitly requested immediate encoding IMM=WORD.
     IiDispatchImmSize BYTE=.ib:; Immediate operand fits to a byte.
.iw: IiEmitOpcode 0x68
     IiEmitImm Operand1, WORD
     RET
.imm:IiRequire 186
     IiRemoveREXW
     IiImmSize Operand1           ; Propose II.MfgImplicit from the immediate number magnitude.
     CMPB [EDI+II.Operand1+EXP.Status],'P'
     JE .ig:
     CMPB [EDI+II.Operand1+EXP.Status],'A'
     JNE .is:
     JSt [EDI+II.Operand1+EXP.Status],expPara,.ig:
     IiReloc iiRelocImmAbs
     JMP .ia:
 .ig:IiReloc iiRelocPara
 .ia:IiDispatchData WORD=.iw:
     JMP .id:
 .is:IiDispatchData WORD=.immW:, DWORD=.immD:
     IiAbortIfNot64               ; Operand-size 64 is allowed in 64bit mode only.
     IiDispatchImm DWORD=.id:     ; Explicitly requested immediate encoding IMM=DWORD.
     IiDispatchImmSize BYTE=.ib:  ; Immediate operand fits to a byte.
     JMP .id:
.Sreg:
    IiDispatchData WORD=.SG:,QWORD=.SG:
    IiAbortIf64
.SG:MOV AL,[EDI+II.Operand1+EXP.Low]
    AND EAX,7 ; Segment register ordinal number 0..5.
    SHL EAX,3
    CMP AL,4<<3 ; Test if Operand1 is ES,CS,SS,DS.                                                        ; >>
    JAE .FSGS:
    IiAbortIf64 
    OR AL,0x06
    IiEmitOpcode EAX
    RET
.FSGS:
    OR AL,0xA0
    IiEmitOpcode 0x0F,EAX
    IiRemoveREXW
    RET
 ENDP IigPUSH::
↑ PUSHW
Push WORD
Tested by
t3191 t3192
IigPUSHW:: PROC
    IiSuffixed PUSH,W
 ENDP IigPUSHW::
↑ PUSHD
Push DWORD
Tested by
t3191 t3192
IigPUSHD:: PROC
    IiSuffixed PUSH,D
 ENDP IigPUSHD::
↑ PUSHQ
Push QWORD
Tested by
t3191 t3192
IigPUSHQ:: PROC
    IiSuffixed PUSH,Q
 ENDP IigPUSHQ::
↑ PUSHA
Push All General-Purpose Registers
Description
PUSHA
Category
gen,stack
Operands
AX,CX,DX,...
Opcode
0x60
CPU
01+
Tested by
t3191
IigPUSHA:: PROC
    IiRequire 186
    IiAbortIf64
    IiDataSize Operand1, UseSegment=ON
    IiEmitOpcode 0x60
    IiDispatchFormat none
.none:RET
 ENDP IigPUSHA::
↑ PUSHAW
Push All WORD general-purpose registers
Tested by
t3191
IigPUSHAW:: PROC
    IiSuffixed PUSHA,W
 ENDP IigPUSHAW::
↑ PUSHAD
Push All DWORD general-purpose registers
Description
PUSHAD
Category
gen,stack
Operands
EAX,ECX,EDX,...
Opcode
0x60
CPU
03+
Tested by
t3191
IigPUSHAD:: PROC
    IiSuffixed PUSHA,D
 ENDP IigPUSHAD::
↑ PUSHF
Push FLAGS Register onto the Stack
Description
PUSHF
Category
gen,stack flgctrl
Operands
Fwo | Fws
Opcode
0x9C | 0x9C
Tested by
t3191
IigPUSHF:: PROC
    IiDataSize UseSegment=ON
    IiRemoveREXW
    IiEmitOpcode 0x9C
    IiDispatchFormat none
.none:RET
 ENDP IigPUSHF::
↑ PUSHFW
Push WORD Flags
Tested by
t3191
IigPUSHFW:: PROC
    IiSuffixed PUSHF,W
 ENDP IigPUSHFW::
↑ PUSHFD
Push DWORD EFlags
Description
PUSHFD
Category
gen,stack flgctrl
Operands
Fdo
Opcode
0x9C
CPU
03+
Tested by
t3191
IigPUSHFD:: PROC
    IiSuffixed PUSHF,D
 ENDP IigPUSHFD::
↑ PUSHFQ
Push QWORD RFlags
Category
gen,stack flgctrl
Operands
Fqs
Opcode
0x9C
CPU
P4+
Tested by
t3191
IigPUSHFQ:: PROC
    IiSuffixed PUSHF,Q
 ENDP IigPUSHFQ::
↑ POP
Pop a Value from the Stack
Description
POP
Category
gen,stack segreg
Operands
ES | CS | SS | DS | Zv | Zvq | Ev | Evq | FS | GS
Opcode
0x07 ^sr | 0x0F ^sR | 0x17 ^Sr | 0x1F ^SR | 0x58 ^+r | 0x58 ^+r | 0x8F ^W /0 | 0x8F ^W /0 | 0x0FA1 ^Sre | 0x0FA9 ^SrE
Tested by
t3195 t3196
IigPOP:: PROC
    IiDataSize Operand1, UseSegment=ON
    IiOpEn M
    IiDispatchFormat r32, r64, r8:, r16, m32, m64, m16, m8, Sreg
.r8:
.m8: IiAbort '6753' ; 8bit register or memory operand cannot be pushed/popped.
.m32:IiAbortIf64
.m16:
.m64:IiEmitOpcode 0x8F
     IiModRM /0
     IiRemoveREXW
     RET
.reg:IiEncoding CODE=LONG     
     JMP .m16:
.r32:IiAbortIf64
.r16:
.r64:IiAllowModifier CODE
     IiDispatchCode LONG=.reg:
     IiEncoding CODE=SHORT
     IiModRM /3
     SetSt [EDI+II.Ppg],iiPpgMod01
     IiRemoveREXW
     RET
.Sreg:
    IiDispatchData WORD=.SG:,QWORD=.SG:
    IiAbortIf64
.SG:MOV AL,[EDI+II.Operand1+EXP.Low]
    AND EAX,7 ; Segment register ordinal number 0..5.
    SHL EAX,3
    CMP AL,4<<3 ; Test if Operand1 is FS,GS.
    JAE .FSGS:
    CMP AL,1<<3 ; Test if Operand1 is CS.                                                        ; >>
    IiAbort cc=E,'6537' ; MOV CS / POP CS is an invalid operation.
    IiAbortIf64 
    OR AL,0x07
    IiEmitOpcode EAX
    RET
.FSGS:
    OR AL,0xA1
    IiEmitOpcode 0x0F,EAX
    IiRemoveREXW
    RET
 ENDP IigPOP::
↑ POPW
Pop WORD
Tested by
t3195 t3196
IigPOPW:: PROC
    IiSuffixed POP,W
 ENDP IigPOPW::
↑ POPD
Pop DWORD
Tested by
t3195 t3196
IigPOPD:: PROC
    IiSuffixed POP,D
 ENDP IigPOPD::
↑ POPQ
Pop QWORD
Tested by
t3195 t3196
IigPOPQ:: PROC
    IiSuffixed POP,Q
 ENDP IigPOPQ::
↑ POPA
Pop All General-Purpose Registers
Description
POPA
Category
gen,stack
Operands
DI,SI,BP,...
Opcode
0x61
CPU
01+
Tested by
t3195
IigPOPA:: PROC
    IiRequire 186
    IiAbortIf64
    IiDataSize Operand1, UseSegment=ON
    IiEmitOpcode 0x61
    IiDispatchFormat none
.none:RET
 ENDP IigPOPA::
↑ POPAW
Pop All WORD general-purpose registers
Tested by
t3195
IigPOPAW:: PROC
    IiSuffixed POPA,W
 ENDP IigPOPAW::
↑ POPAD
Pop All DWORD general-purpose registers
Description
POPAD
Category
gen,stack
Operands
EDI,ESI,EBP,...
Opcode
0x61
CPU
03+
Tested by
t3195
IigPOPAD:: PROC
    IiSuffixed POPA,D
 ENDP IigPOPAD::
↑ POPF
Pop Stack into FLAGS Register
Description
POPF
Category
gen,stack flgctrl
Operands
Fwo | Fws
Opcode
0x9D | 0x9D
Tested by
t3195
IigPOPF:: PROC
    IiDataSize UseSegment=ON
    IiRemoveREXW
    IiEmitOpcode 0x9D
    IiDispatchFormat none
.none:RET
 ENDP IigPOPF::
↑ POPFW
Pop WORD Flags
Tested by
t3195
IigPOPFW:: PROC
    IiSuffixed POPF,W
 ENDP IigPOPFW::
↑ POPFD
Pop DWORD EFlags
Description
POPFD
Category
gen,stack flgctrl
Operands
Fdo
Opcode
0x9D
CPU
03+
Tested by
t3195
IigPOPFD:: PROC
    IiSuffixed POPF,D
 ENDP IigPOPFD::
↑ POPFQ
Pop QWORD RFlags
Description
POPFQ
Category
gen,stack flgctrl
Operands
Fqs
Opcode
0x9D
CPU
P4+
Tested by
t3195
IigPOPFQ:: PROC
    IiSuffixed POPF,Q
 ENDP IigPOPFQ::
↑ MOV
Copy to destination from source
Description
MOV (general-purpose registers)
MOVQ (XMM registers)
MOV (control registers)
MOV (debug registers)
Category
gen,datamov
Operands
Eb,Gb | Evqp,Gvqp | Gb,Eb | Gvqp,Evqp | Mw,Sw | Rvqp,Sw | Sw,Ew | AL,Ob | rAX,Ovqp | Ob,AL | Ovqp,rAX | Zb,Ib | Zvqp,Ivqp | Eb,Ib | Evqp,Ivds | Rd,Cd | Hd,Cd | Rq,Cq | Hq,Cq | Rd,Dd | Hd,Dd | Rq,Dq | Hq,Dq | Cd,Rd | Cd,Hd | Cq,Rq | Cq,Hq | Dd,Rd | Dq,Hq | Dq,Rq | Dq,Hq | Rd,Td | Hd,Td | Td,Rd | Td,Hd
Opcode
0x88 ^dw /r | 0x89 ^dW /r | 0x8A ^Dw /r | 0x8B ^Dw /r | 0x8C ^d /r | 0x8C ^d /r | 0x8E ^D /r | 0xA0 ^w | 0xA1 ^W | 0xA2 ^w | 0xA3 ^W | 0xB0 ^+r | 0xB8 ^+r | 0xC6 ^w /0 | 0xC7 ^W /0 | 0x0F20 /r | 0x0F20 /r | 0x0F20 /r | 0x0F20 /r | 0x0F21 /r | 0x0F21 /r | 0x0F21 /r | 0x0F21 /r | 0x0F22 /r | 0x0F22 /r | 0x0F22 /r | 0x0F22 /r | 0x0F23 /r | 0x0F23 /r | 0x0F23 /r | 0x0F23 /r | 0x0F24 /r | 0x0F24 /r | 0x0F26 /r | 0x0F26 /r
Tested by
t3041 t3042 t3043
IigMOV:: PROC
       IiAllowModifier CODE, DISP, ADDR, IMM
       Dispatch DL,Sreg,mmx,xmm,imm ; Auxilliary format dispatcher of the last operand.
       Dispatch DH,Sreg,mmx,xmm  ; Auxilliary format dispatcher of the last but one operand.
       IiDataSize
       IiDispatchFormat                    \  
       r8.r8, r16.r16, r32.r32, r64.r64,   \
       r8.m8, r16.m16, r32.m32, r64.m64,   \
       m8.r8, m16.r16, m32.r32, m64.r64,   \
       r32.ctr, r64.ctr, ctr.r32, ctr.r64, \
       r32.ct8, r64.ct8, ct8.r32, ct8.r64, \
       r32.dgr, r64.dgr, dgr.r32, dgr.r64, \
       r32.tsr, tsr.r32
.mr8L: IiEncoding CODE=LONG
.mr8:  IiEmitOpcode 0x88
       IiOpEn MR
       IiModRM /r
       RET
.rm8L: IiEncoding CODE=LONG
       IiEmitOpcode 0x8A
       IiOpEn RM
       IiModRM /r
       RET
.r8.r8:IiDispatchCode LONG=.rm8L:
.mr8S: IiEncoding CODE=SHORT,ADDR=ABS
       JMP .mr8:
.r8.m8:IiDispatchNotAccum Operand1, .rm8L:
       IiDispSize Operand2
       JC .rm8L:
       IiAllowPrefix SegAny086
       IiEncoding CODE=SHORT,ADDR=ABS
       IiEmitOpcode 0xA0
       RET
.m8.r8:IiDispatchNotAccum Operand2, .mr8S:
       IiDispatchCode LONG=.mr8L:
       IiDispSize Operand1
       JC .mr8S:
       IiAllowPrefix SegAny086
       IiEncoding CODE=SHORT,ADDR=ABS
       IiEmitOpcode 0xA2
       RET
.mrWL: IiEncoding CODE=LONG
.mrW:  IiEmitOpcode 0x89
       IiOpEn MR
       IiModRM /r
       RET
.rmWL: IiEncoding CODE=LONG
       IiEmitOpcode 0x8B
       IiOpEn RM
       IiModRM /r
       RET
.r16.r16:
.r32.r32:
.r64.r64:
       IiDispatchCode LONG=.rmWL:
.mrWS: IiEncoding CODE=SHORT
       JMP .mrW:
.r16.m16:
.r32.m32:
.r64.m64:
       IiDispatchNotAccum Operand1, .rmWL:
       IiDispSize Operand2
       JC .rmWL:
       IiAllowPrefix SegAny086
       IiEncoding CODE=SHORT,ADDR=ABS
       IiEmitOpcode 0xA1
       RET
.m16.r16:
.m32.r32:
.m64.r64:
       IiDispatchNotAccum Operand2, .mrWL:
       IiDispSize Operand1
       JC  .mrWL:
       IiAllowPrefix SegAny086
       IiEncoding CODE=SHORT,ADDR=ABS
       IiEmitOpcode 0xA3
       RET
.r32.ct8:
       IiRequire AMD
       IiAllowPrefix LOCK
       IiEmitPrefix LOCK
       IiRemoveREXR
.r32.ctr:
       IiAbortIf64
  .rc: IiEmitOpcode 0x0F,0x20
       IiOpEn MR
       IiModRM /r
       IiRemoveREXW
       IiRemoveOTOGGLE
       RET
.r64.ct8:
.r64.ctr:
       IiAbortIfNot64
       JMP .rc:
.ct8.r32:
       IiRequire AMD
       IiAllowPrefix LOCK
       IiEmitPrefix LOCK
       IiRemoveREXR
.ctr.r32:
       IiAbortIf64
 .cr:  IiEmitOpcode 0x0F,0x22
       IiOpEn RM
       IiModRM /r
       IiRemoveREXW
       IiRemoveOTOGGLE
       RET
.ct8.r64:
.ctr.r64:
       IiAbortIfNot64
       JMP .cr:
.r32.dgr:
       IiAbortIf64
  .rd: IiEmitOpcode 0x0F,0x21
       IiOpEn MR
       IiModRM /r
       IiRemoveREXW
       IiRemoveOTOGGLE
       RET
.r64.dgr:
       IiAbortIfNot64
       JMP .rd:
.dgr.r32:
       IiAbortIf64
  .dr: IiEmitOpcode 0x0F,0x23
       IiOpEn RM
       IiModRM /r
       IiRemoveREXW
       IiRemoveOTOGGLE
       RET 
.dgr.r64:
       IiAbortIfNot64
       JMP .dr:
.r32.tsr:
       IiAbortIf64
       IiEmitOpcode 0x0F,0x24
       IiOpEn MR
       IiModRM /r
       IiRemoveOTOGGLE
       RET 
.tsr.r32:              
       IiAbortIf64
       IiEmitOpcode 0x0F,0x26
       IiOpEn RM
       IiModRM /r
       IiRemoveOTOGGLE
       RET 
.imm:  IiOpEn M           ; The last MOV operand is immediate.
       IiImmSize Operand2
       CMPD [EDI+II.Operand2+EXP.Seg],0
       JZ .is: ; If scalar immediate.
       JSt [EDI+II.Operand2+EXP.Status],expPara,.ig:
       IiReloc iiRelocImmAbs
       JMP .is:
  .ig: IiReloc iiRelocPara
  .is: IiDataSize Operand1, SpecifyMem=ON
       IiDispatchFormat r8.imm, r16.imm, r32.imm, r64.imm,  \
                        m8.imm, m16.imm, m32.imm, m64.imm
.m8.imm:
       IiEmitImm Operand2, BYTE
       IiEncoding CODE=LONG
       IiEmitOpcode 0xC6
       IiModRM /0
       RET
.r8.imm:
       IiDispatchCode LONG=.m8.imm:
       IiEncoding CODE=SHORT
       SetSt [EDI+II.Ppg],iiPpgMod10 ; Change ModRM byte 0xF0+r to opcode byte 0xB0+r.
       IiModRM /6
       IiEmitImm Operand2, BYTE
       RET                                
.m16.imm:
       IiEmitImm Operand2, WORD
  .CL: IiEncoding CODE=LONG
       IiEmitOpcode 0xC7
       IiModRM /0
       RET
.m32.imm:
.m64.imm:  
       IiEmitImm Operand2, DWORD
       JMP .CL:
.r16.imm:
       IiDispatchCode LONG=.m16.imm:
       IiEmitImm Operand2, WORD
  .CS: IiEncoding CODE=SHORT
       SetSt [EDI+II.Ppg],iiPpgMod10 ; Change ModRM byte 0xF8+r to opcode byte 0xB8+r.
       IiModRM /7 
       RET                         
.r32.imm:
       IiDispatchCode LONG=.m32.imm:
  .ID: IiEmitImm Operand2, DWORD
       IiRemoveREXW
       JMP .CS:
  .IQ: IiEmitImm Operand2, QWORD
       JMP .CS:
.r64.imm:
       IiDispatchImm QWORD=.IQ: ; If explicitly requested IMM=QWORD.
       MOV EDX,[EDI+II.Operand2+EXP.High]
       MOV EAX,[EDI+II.Operand2+EXP.Low]
       TEST EDX ; Does unsigned immediate fit to 32 bits? 
       JZ .Z:
       INC EDX ; Does signed immediate fit to 32 bits? 
       JNZ .IQ:
       TEST EAX
       JNS .IQ:
       IiDispatchCode SHORT=.IQ:
       JMP .m64.imm:
  .ZL: TEST EAX
       JS .ID:
       JMP .m64.imm:     
  .Z:  IiDispatchCode LONG=.ZL:
       JMP .ID:   
.Sreg: IiDataSize UseSegment=ON
       IiDispatchFormat r16.Sreg, r32.Sreg, r64.Sreg, \
                        m16.Sreg, m32.Sreg, m64.Sreg, \
                        Sreg.r16, Sreg.r32, Sreg.r64, \
                        Sreg.m16, Sreg.m32, Sreg.m64
.r16.Sreg:
.r32.Sreg:
.r64.Sreg:
.m16.Sreg:
.m32.Sreg:
.m64.Sreg:
       IiEmitOpcode 0x8C
       IiOpEn MR
       IiModRM /r
       RET
.Sreg.r16:
.Sreg.r32:
.Sreg.r64:
.Sreg.m16:
.Sreg.m32:
.Sreg.m64:
       RstSt [EDI+II.MfgEmitted],iiMfgDATA_Mask
       IiEncoding DATA=WORD
       CMPB [EDI+II.Operand1+EXP.Low],iiReg_SEG+1 ; Check if Operand1 is CS.
       IiAbort cc=E,'6537' ; MOV CS / POP CS is an invalid operation.
       IiEmitOpcode 0x8E
       IiOpEn RM
       IiModRM /r
       IiRemoveREXW
       IiRemoveOTOGGLE
       RET
.mmx:    ; Suffix D or Q is mandatory when copying to/from MMX register.
         IiEmitOpcode 0x0F
         IiModRM /r
         IiDispatchSuffix D=.mmxD:, Q=.mmxQ:
.E7513:  IiAbort '7513' ; This operand combination requires mnemonic suffix ~D or ~Q.
.mmxD:   IiEncoding DATA=DWORD,CODE=SHORT
         IiDispatchFormat mmx.r32, r32.mmx, mmx.mem, mem.mmx
.mmx.r32:IiEmitOpcode 0x6E
         IiOpEn RM
         RET
.r32.mmx:IiEmitOpcode 0x7E
         IiOpEn MR
         RET
.mmxQ:   IiEncoding DATA=QWORD
         IiDispatchFormat mmx.mmx, mmx.r64, r64.mmx, mmx.mem, mem.mmx
.mmx.r64:IiEncoding CODE=LONG
         IiEmitPrefix REX.W
         IiEmitOpcode 0x6E
         IiOpEn RM
         RET
.mmx.mem:IiDispatchSuffix D=.mmx.r32:
         IiDispatchCode LONG=.mmx.r64:
         IiEncoding CODE=SHORT
         IiEmitOpcode 0x6F
         IiOpEn RM
         RET
.r64.mmx:IiEncoding CODE=LONG
         IiEmitPrefix REX.W
         IiEmitOpcode 0x7E
         IiOpEn MR
         RET
.mem.mmx:IiDispatchSuffix D=.r32.mmx:
         IiDispatchCode LONG=.r64.mmx:
         IiEncoding CODE=SHORT
.memmm:  IiEmitOpcode 0x7F
         IiOpEn MR
         RET
.memmmL: IiEncoding CODE=LONG
         JMP .memmm:
.mmx.mmx:IiDispatchCode LONG=.memmmL:
         IiEncoding CODE=SHORT
         IiEmitOpcode 0x6F
         IiOpEn RM
         RET
.xmm:    ; Suffix D or Q is mandatory when copying to/from XMM register.
         IiEmitOpcode 0x0F
         IiModRM /r
         IiDispatchSuffix D=.xmmD:, Q=.xmmQ:
         JMP .E7513: ; This operand combination requires mnemonic suffix ~D or ~Q.
.xmmD:   IiEncoding DATA=DWORD,CODE=SHORT
         IiDispatchFormat xmm.r32, r32.xmm, xmm.mem, mem.xmm
.xmm.r32:IiEmitPrefix OTOGGLE
         IiEmitOpcode 0x6E
         IiOpEn RM
         RET
.r32.xmm:IiEmitPrefix OTOGGLE
         IiEmitOpcode 0x7E
         IiOpEn MR
         RET
.xmmQ:   IiEncoding DATA=QWORD
         IiDispatchFormat xmm.xmm, xmm.r64, r64.xmm, xmm.mem, mem.xmm
.xmm.r64:IiEncoding CODE=LONG
         IiEmitPrefix OTOGGLE, REX.W
         IiEmitOpcode 0x6E
         IiOpEn RM
         RET
.xmm.mem:IiDispatchSuffix D=.xmm.r32:
         IiDispatchCode LONG=.xmm.r64:
         IiEncoding CODE=SHORT
         IiEmitPrefix REPE
         IiEmitOpcode 0x7E
         IiOpEn RM
         RET
.r64.xmm:IiEncoding CODE=LONG
         IiEmitPrefix OTOGGLE, REX.W
         IiEmitOpcode 0x7E
         IiOpEn MR
         RET
.mem.xmm:IiDispatchSuffix D=.r32.xmm:
         IiDispatchCode LONG=.r64.xmm:
         IiEncoding CODE=SHORT
.memxmm: IiEmitPrefix OTOGGLE
         IiEmitOpcode 0xD6
         IiOpEn MR
         RET
.memxmmL:IiEncoding CODE=LONG
         JMP .memxmm:
.xmm.xmm:IiDispatchCode LONG=.memxmmL:
         IiEncoding CODE=SHORT
         IiEmitPrefix REPE
         IiEmitOpcode 0x7E
         IiOpEn RM
         RET
 ENDP IigMOV::
↑ MOVB
Copy BYTE
Tested by
t3041 t3042 t3043
IigMOVB:: PROC
    IiSuffixed MOV,B
 ENDP IigMOVB::
↑ MOVW
Copy WORD
Tested by
t3041 t3042 t3043
IigMOVW:: PROC
    IiSuffixed MOV,W
 ENDP IigMOVW::
↑ MOVD
Copy DWORD
Description
MOVD
Category
mmx,datamov
Operands
Pq,Ed | Pq,Ed | Vdq,Ed | Vdq,Ed | Ed,Pq | Ed,Pq | Ed,Vdq | Ed,Vdq
Opcode
0x0F6E /r | 0x0F6E /r | 0x660F6E /r | 0x660F6E /r | 0x0F7E /r | 0x0F7E /r | 0x660F7E /r | 0x660F7E /r
CPU
PX+
Tested by
t3041 t3042 t3043
IigMOVD:: PROC
    IiSuffixed MOV,D
 ENDP IigMOVD::
↑ MOVQ
Copy QWORD
Description
MOVQ
Category
mmx,datamov
Operands
Pq,Eqp | Vdq,Eqp | Eqp,Pq | Eqp,Edq | Pq,Qq | Vq,Wq | Qq,Pq | Wq,Vq
Opcode
0x0F6E /r | 0x660F6E /r | 0x0F7E /r | 0x660F7E /r | 0x0F6F /r | 0xF30F7E /r | 0x0F7F /r | 0x660FD6 /r
CPU
P4+
Documented
D31
Tested by
t3041 t3042 t3043
IigMOVQ:: PROC
    IiSuffixed MOV,Q
 ENDP IigMOVQ::
↑ MOVSX
Copy Sign-Extended
Description
MOVSX
Category
gen,conver
Operands
Gvqp,Eb | Gvqp,Ew
Opcode
0x0FBE ^Dw /r | 0x0FBF ^DW /r
CPU
03+
Tested by
t3201
IigMOVSX:: PROC
         MOV AL,0xBE ; Opcode for BYTE version of MOVSX.
.op:     IiRequire 386
         IiOpEn RM
         IiModRM /r
         CMP DH,r16
         JNE .10:
         IiDataSize BYTE
         JMP .20:
    .10: IiDataSize Operand2 ; Displayed operand-size is specified by Operand2/suffix/modifier. 
    .20: IiRemoveOTOGGLE     ; Prefixes-encoded operand-size will be specified later by Operand1. 
         IiRemoveREXW
         IiDispatchFormat r16.r8,r16.m8, r32.r8,r32.m8,r32.r16,r32.m16, \
                          r64.r8,r64.m8,r64.r16,r64.m16,r64.r32,r64.m32
.r16.r8:
.r16.m8: IiDispatchWidth BITS16=.Op:
.OTOGGLE:IiEmitPrefix OTOGGLE
  .Op:   IiEmitOpcode 0x0F,EAX
         RET
.r32.r16:
.r32.m16:INC EAX ; Change opcode from 0xBE to 0xBF (MOVSX) or from 0xB6 to 0xB7 (MOVZX).
.r32.r8:
.r32.m8: IiDispatchWidth BITS16=.OTOGGLE:
         JMP .Op:
.r64.r16:
.r64.m16:INC EAX ; Change opcode from 0xBE to 0xBF.
.r64.r8:
.r64.m8: IiEmitPrefix REX.W
         JMP .Op:
 .MOVZXD:IiEmitOpcode 0x8B ; MOVZXD r64,r/m32 encode as MOV r32,r/m32 in 64bit mode.
         RET        
.r64.r32:
.r64.m32:CMP AL,0xB6
         JE .MOVZXD:
         IiEmitPrefix REX.W
         IiEmitOpcode 0x63 ; MOVSXD r64,r/m32
         RET  
     ENDP IigMOVSX::
↑ MOVSXB
Copy Sign-extended BYTE
Tested by
t3201
IigMOVSXB:: PROC
       IiSuffixed MOVSX,B
     ENDP IigMOVSXB::
↑ MOVSXW
Copy Sign-extended WORD
Tested by
t3201
IigMOVSXW:: PROC
       IiSuffixed MOVSX,W
     ENDP IigMOVSXW::
↑ MOVSXD
Copy Sign-Extended DWORD
Description
MOVSXD
Category
gen,conver
Operands
Gdqp,Ed
Opcode
0x63 ^D /r
CPU
P4+
Tested by
t3201
IigMOVSXD:: PROC
       IiSuffixed MOVSX,D
     ENDP IigMOVSXD::
↑ MOVZX
Copy Zero-Extended
Description
MOVZX
Category
gen,conver
Operands
Gvqp,Eb | Gvqp,Ew
Opcode
0x0FB6 ^Dw /r | 0x0FB7 ^DW /r
CPU
03+
Tested by
t3201
IigMOVZX:: PROC
         MOV AL,0xB6 ; Opcode for BYTE version of MOVZX.
         JMP IigMOVSX.op:
     ENDP IigMOVZX::
↑ MOVZXB
Copy Zero-extended BYTE
Tested by
t3201
IigMOVZXB:: PROC
       IiSuffixed MOVZX,B
     ENDP IigMOVZXB::
↑ MOVZXW
Copy Zero-extended WORD
Tested by
t3201
IigMOVZXW:: PROC
       IiSuffixed MOVZX,W
     ENDP IigMOVZXW::
↑ MOVZXD
Copy Zero-extended DWORD
Operands
r64, r/m32
Opcode
89
CPU
X64
Tested by
t3201
IigMOVZXD:: PROC
    IiSuffixed MOVZX,D
  ENDP IigMOVZXD::
↑ UMOV
User Move Data
Category
UNDOC
Operands
r,r/mem || r/mem,r
Opcode
0x0F10 || 0x0F11 || 0x0F12 || 0x0F13
CPU
386 AMD
Documented
rcollins.org
Tested by
t3148
IigUMOV:: PROC
    IiRequire 386,AMD,UNDOC
    IiAllowModifier CODE
    IiDataSize SpecifyMem=OFF
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat r8.r8,r8.mem,mem.r8,r16.r16,r16.mem,mem.r16, \
                     r32.r32,r32.mem,mem.r32,r64.r64,r64.mem,mem.r64
.r8.mem:
    IiEncoding CODE=LONG
    IiOpEn RM
    IiEmitOpcode 0x12
    RET
.r8.r8:
    IiDispatchCode LONG=.r8.mem:
.mem.r8:
    IiEncoding CODE=SHORT
    IiOpEn MR
    IiEmitOpcode 0x10
    RET
.r16.mem:
.r32.mem:
.r64.mem:
    IiEncoding CODE=LONG
    IiOpEn RM
    IiEmitOpcode 0x13
    RET
.r16.r16:
.r32.r32:
.r64.r64:
    IiDispatchCode LONG=.r16.mem:
.mem.r16:
.mem.r32:
.mem.r64:
    IiEncoding CODE=SHORT
    IiOpEn MR
    IiEmitOpcode 0x11
    RET
 ENDP IigUMOV::
↑ CALL
Call Procedure
Description
CALL
Category
gen,branch stack
Operands
Jvds | Ev | Eq
Opcode
0xE8 | 0xFF /2 | 0xFF /2
Documented
D41
Tested by
t3161 t3162 t3163
Invokes
IiRelocSizeRIP
IigCALL:: PROC
     IiAllowModifier DIST, DATA
     IiOpEn M
     IiDataSize Operand1,UseSegment=ON,SpecifyMem=OFF
     IiRemoveREXW
     IiDispatchFormat imm,mem,far,r16,r32,r64
.r32:
.r16:IiAbortIf64
 .mn:IiEncoding DIST=NEAR,ADDR=ABS ; Indirect absolute CALLN [mem] or CALLN reg.
     IiEmitOpcode 0xFF
     IiModRM /2
     RET
.r64:IiAbortIfNot64
     JMP .mn:
.mem:IiDispatchDist FAR=.mf:
     IiDispatchData QWORD=.r64:
     JMP .r32:
 .mf:IiEncoding DIST=FAR,ADDR=ABS ; Indirect absolute CALLF [mem].
     IiEmitOpcode 0xFF
     IiModRM /3
     IiDispatchData QWORD=.RXW:
     RET
.RXW:IiEmitPrefix REX.W
     RET
.imm: ; Direct CALL immediate address. May be changed to FAR when groups do not match or on explicit request.
     RstSt [EDI+II.MfgEmitted],iiMfgDATA_Mask ; Operand-size detected by IiDataSize from segment-width may be overwritten.
     IiDispatchDist FAR=.far:,NEAR=.in: ; Dispatch explicit suffixed or explicit DIST= request.
     JSt [EDI+II.Operand1+EXP.Status],expFar,.far: ; If the target is PROC DIST=FAR.
 .in:IiDispatchLocation [EDI+II.Operand1+EXP.Seg],RIP=.rip:, NEAR=.near: ; Dispatch by segments difference.
     IiDispatchDist NEAR=.near:
.far:; FAR absolute or relative transfer. Target is specified as
     ; 1) scalar,  direct  imm  far, encoded as CALLF immPara:immOffset ; no relocation,
     ; 2) explicit DIST=FAR request, encoded as CALLF PARA#target:OFFSET#target ; iiRelocFar=relocPara+relocAbsVA.
     IiAbortIf64    ; Direct absolute CALLF segregvalue:offset (immediate value).
     IiEmitOpcode 0x9A
     IiImmSize Operand1 ; Prepare operand and propose imm size into II.MfgImplicit by operand magnitude.
     CMPB [EDI+II.Operand1+EXP.Status],'F' ; Is the target specified as absolute scalars?
     JE .fAbs:
     IiReloc iiRelocFar ; Calling a far target requires relocation of both segment:offset values.
.fAbs:SetSt [EDI+II.Ppg],iiPpgPara ; Ask IiFlush to emit 16bit paragraph address from II.Para.
     IiDispatchWidth BITS32=.f32:
     ; Calling from 16bit segment.
     IiDispatchData WORD=.fW:, DWORD=.fOD: ; If explicit DATA= modifier in 16bit mode.
     IiDispatchImm     DWORD=.fOD: ; If explicit IMM=DWORD modifier in 16bit mode.
     IiDispatchImmSize DWORD=.fOD: ; If immediate offset over 64K in 16bit mode.
.fW: IiEncoding DIST=FAR,ADDR=ABS,DATA=WORD,IMM=WORD
     RET
.fOW:IiEmitPrefix OTOGGLE
     JMP .fW:
.f32:IiDispatchData DWORD=.fD:, WORD=.fOW: ; Calling from 32bit segment.
     IiDispatchImm  WORD=.fOW: ; If explicitly requested IMM=WORD.
.fD: IiEncoding DIST=FAR,ADDR=ABS,DATA=DWORD,IMM=DWORD
     RET
.fOD:IiEmitPrefix OTOGGLE
     JMP .fD:
.near: ; Direct relative CALLN offset with relocation, resolved at link time.
     IiDispatchDist FAR=.far:
     IiImmSize Operand1
     IiReloc iiRelocImmRel
     MOV EAX,[EDI+II.MfgImplicit]
     ; Immediate number or address is still stored in [EDI+II.Imm] as an original absolute value,
     ; the actual RIP subtraction and emitting will take place in IiFlush.
     JMP .n:
.rip: ; Direct rIP-relative CALLN offset, relocation resolved at assembly time.
     IiImmSize Operand1
     IiReloc iiRelocImmRIP
     Invoke IiRelocSizeRIP::,EDI,EBX ; Inspect Imm-RIP magnitude and return it as iiMfgIMM_Mask to EAX.
.n:  IiEmitOpcode 0xE8
    ; Returned operand-size in EAX can be autoprolonged from 16 bits when relative target distance exceedes 64K,
    ; or if explicitly requested IMM=DWORD or DATA=DWORD, or if in 64bit mode.
    ; Immediate number or address is still stored in [EDI+II.Imm] as an original absolute value,
    ; the actual RIP subtraction and emitting will take place in IiFlush.
     IiDispatchWidth BITS16=.n16, BITS64=.n64:
     ; Current mode is 32bit.
     JSt EAX,iiMfgIMM_DWORD|iiMfgIMM_QWORD,.nD: ; The distance is above 64K, it cannot be overriden to 16bit operand-size.
     IiDispatchData DWORD=.nD:, WORD=.nOW: ; Accept explicit DATA= modifier.
     IiDispatchImm  WORD=.nOW:             ; Accept explicit IMM= modifier.
.nD: IiEncoding DIST=NEAR,ADDR=REL,DATA=DWORD,IMM=DWORD
     RET
.n64:IiEncoding DIST=NEAR,ADDR=REL,DATA=QWORD,IMM=DWORD
     IiAbortIfNot64
     RET
.n16:; Current segment is 16bit.
     JSt EAX,iiMfgIMM_DWORD|iiMfgIMM_QWORD,.nOD: ; If the distance is above 64K, it will be prolonged to 32bit operand-size.
     IiDispatchData DWORD=.nOD:, QWORD=.n64: ; Accept explicit DATA= modifier.
     IiDispatchImm  DWORD=.nOD:              ; Accept explicit IMM= modifier.
.nW: IiEncoding DIST=NEAR,ADDR=REL,DATA=WORD,IMM=WORD
     RET
.nOW:IiEmitPrefix OTOGGLE
     JMP .nW:
.nOD:IiEmitPrefix OTOGGLE
     JMP .nD:
    ENDP IigCALL
↑ CALLN
Near procedure call
Tested by
t3161 t3162 t3163
IigCALLN:: PROC
    IiSuffixed CALL,N
 ENDP IigCALLN::
↑ CALLF
Far procedure call
Category
gen,branch stack
Operands
Ap | Mptp
Opcode
0x9A | 0xFF /3
Tested by
t3161 t3162 t3163
IigCALLF:: PROC
    IiSuffixed CALL,F
 ENDP IigCALLF::
↑ JMP
Jump
Description
JMP
Category
gen,branch
Operands
Jvds | Jbs | Ev | Eq
Opcode
0xE9 | 0xEB | 0xFF /4 | 0xFF /4
Documented
D41
Tested by
t3141 t3142 t3143
Invokes
IiRelocSizeRIP
IigJMP:: PROC
     IiAllowModifier DIST, DATA
     IiOpEn M
     IiDataSize Operand1,UseSegment=ON,SpecifyMem=OFF
     IiRemoveREXW
     IiDispatchFormat imm,mem,far,r16,r32,r64
.r32:
.r16:IiAbortIf64
 .mn:IiEncoding DIST=NEAR,ADDR=ABS ; Indirect absolute JMPN [mem] or JMPN reg.
     IiEmitOpcode 0xFF
     IiModRM /4
     RET
.r64:IiAbortIfNot64
     JMP .mn:
.mem:IiDispatchDist FAR=.mf:
     IiDispatchData QWORD=.r64:
     JMP .r32:
 .mf:IiEncoding DIST=FAR,ADDR=ABS ; ; Indirect absolute JMPF [mem].
     IiEmitOpcode 0xFF
     IiModRM /5
     IiDispatchData QWORD=.RXW:
     RET
.RXW:IiEmitPrefix REX.W
     RET
.imm: ; Direct JMP immediate address. May be changed to FAR when groups do not match or on explicit request.
     RstSt [EDI+II.MfgEmitted],iiMfgDATA_Mask ; Operand-size detected by IiDataSize from segment-width may be overwritten.
     IiDispatchDist SHORT=.in:,NEAR=.in:,FAR=.far: ; Dispatch explicit suffixed or DIST= request.
     JSt [EDI+II.Operand1+EXP.Status],expFar,.far: ; If the target is PROC DIST=FAR.
     ; Target distance is not explicitly specified. Use the logic in IiDispatchLocation.
.in: IiDispatchLocation [EDI+II.Operand1+EXP.Seg],RIP=.rip:,NEAR=.near: ; Dispatch by segments difference.
.far:; FAR absolute or relative transfer. Target is specified as
     ; 1) scalar,  direct  imm  far, encoded as JMPF immPara:immOffset ; no relocation,
     ; 2) explicit DIST=FAR request, encoded as JMPF PARA#target:OFFSET#target ; iiRelocFar=relocPara+relocAbsVA.
     IiDispatchDist NEAR=.near:
     IiAbortIf64
     IiEmitOpcode 0xEA
     IiImmSize Operand1 ; Prepare operand and propose imm size into II.MfgImplicit by operand magnitude.
     CMPB [EDI+II.Operand1+EXP.Status],'F' ; Is the target specified as absolute scalars?
     JE .fAbs:
     IiReloc iiRelocFar ; Jumping to a far target requires relocation of both segment:offset values.
.fAbs:SetSt [EDI+II.Ppg],iiPpgPara ; Ask IiFlush to emit 16bit paragraph address from II.Para.
     IiDispatchWidth BITS32=.f32:
     ; Jumping from 16bit segment.
     IiDispatchData WORD=.fW:, DWORD=.fOD: ; If explicit DATA= modifier in 16bit mode.
     IiDispatchImm     DWORD=.fOD: ; If explicit IMM= modifier in 16bit mode.
     IiDispatchImmSize DWORD=.fOD: ; If immediate offset over 64K in 16bit mode.
.fW: IiEncoding DIST=FAR,ADDR=ABS,DATA=WORD,IMM=WORD
     RET
.fOW:IiEmitPrefix OTOGGLE
     JMP .fW:
.f32:; Jumping from 32bit segment.
     IiDispatchData DWORD=.fD:, WORD=.fOW:
     IiDispatchImm  WORD=.fOW: ; If explicitly requested IMM=WORD.
.fD: IiEncoding DIST=FAR,ADDR=ABS,DATA=DWORD,IMM=DWORD
     RET
.fOD:IiEmitPrefix OTOGGLE
     JMP .fD:
.near: ; Direct relative JMPN offset with relocation, resolved at link time.
     IiDispatchDist FAR=.far:
     IiImmSize Operand1
     IiReloc iiRelocImmRel
     MOV EAX,[EDI+II.MfgImplicit]
     ; Immediate number or address is still stored in [EDI+II.Imm] as an original absolute value,
     ; the actual RIP subtraction and emitting will take place in IiFlush.
     JMP .n:
.rip: ; Direct relative short or near JMP offset, relocation resolved at assembly time.
     IiImmSize Operand1
     IiReloc iiRelocImmRIP
     Invoke IiRelocSizeRIP::,EDI,EBX  ; Inspect Imm-RIP magnitude and return it as iiMfgIMM_Mask to EAX.
     JSt EAX,iiMfgIMM_BYTE, .short:
 .n: IiEmitOpcode 0xE9 ; Direct relative JMPN offset word/dword with relocation, resolved at link time.
    ; Returned operand-size EAX can be autoprolonged from 16 bits when relative target distance exceedes 64K,
    ; or if explicitly requested IMM=DWORD or DATA=DWORD, or if in 64bit mode.
    ; Immediate number or address is still stored in [EDI+II.Imm] as an original absolute value,
    ; the actual RIP subtraction and emitting will take place in IiFlush.
     IiDispatchWidth BITS16=.n16, BITS64=.n64:
     ; Current segment is 32bit.
     JSt EAX,iiMfgIMM_DWORD|iiMfgIMM_QWORD,.nD: ; If the distance is above 64K, it cannot be overriden to 16bit operand-size.
     IiDispatchData DWORD=.nD:, WORD=.nOW: ; Accept explicit DATA= modifier.
     IiDispatchImm  WORD=.nOW:             ; Accept explicit IMM= modifier.
.nD: IiEncoding DIST=NEAR,ADDR=REL,DATA=DWORD,IMM=DWORD
     RET
.n64:IiEncoding DIST=NEAR,ADDR=REL,DATA=QWORD,IMM=DWORD ; Current segment is 64bit.
     IiAbortIfNot64
     RET
.n16:; Current segment is 16bit.
     JSt EAX,iiMfgIMM_DWORD|iiMfgIMM_QWORD,.nOD: ; If the distance is above 64K, it will be prolonged to 32bit operand-size.
     IiDispatchData DWORD=.nOD:, QWORD=.n64: ; Accept explicit DATA= modifier.
     IiDispatchImm  DWORD=.nOD:              ; Accept explicit IMM= modifier.
.nW: IiEncoding DIST=NEAR,ADDR=REL,DATA=WORD,IMM=WORD
     RET
.nOW:IiEmitPrefix OTOGGLE
     JMP .nW:
.nOD:IiEmitPrefix OTOGGLE
     JMP .nD:
.short:
     IiDispatchDist NEAR=.n:
     IiDispatchData WORD=.n:,DWORD=.n:,QWORD=.n:
     IiDispatchImm WORD=.n:,DWORD=.n:
     IiEmitOpcode 0xEB ; Direct relative short JMPS offset. No relocation.
     IiDispatchWidth BITS64=.sQ:,BITS16=.sW:
     IiEncoding DIST=SHORT,ADDR=REL,IMM=BYTE,DATA=DWORD
     RET
 .sW:IiEncoding DIST=SHORT,ADDR=REL,IMM=BYTE,DATA=WORD
     RET
 .sQ:IiEncoding DIST=SHORT,ADDR=REL,IMM=BYTE,DATA=QWORD
     RET
 ENDP IigJMP::
↑ JMPN
Near jump
Tested by
t3141 t3142 t3143
IigJMPN:: PROC
     IiSuffixed JMP,N
 ENDP IigJMPN::
↑ JMPF
Far jump
Category
gen,branch
Operands
Ap | Mptp
Opcode
0xEA | 0xFF /5
Tested by
t3141 t3142 t3143
IigJMPF:: PROC
      IiSuffixed JMP,F
 ENDP IigJMPF::
↑ JMPS
Short jump
Tested by
t3141 t3142 t3143
IigJMPS:: PROC
      IiSuffixed JMP,S
 ENDP IigJMPS::
↑ LOOP
Decrement count; Jump short if count!=0
Description
LOOP
Category
gen,branch,cond
Operands
eCX,Jbs | rCX,Jbs
Opcode
0xE2 | 0xE2
Remark
LOOP handler is also used for instructions LOOPcc and JrCXZ.
Out of byte-range loop is replaced with three machine instructions:
LOOP $+4 ; Loop to near or far proxy JMP.
JMPS $+JMPsize ; Skip the near or far proxy jump.
JMP %1 ; Near or far proxy jump to the original target.
Tested by
t3171 t3172 t3173
Invokes
IiRelocSizeRIP
IigLOOP:: PROC
       MOV AL,0xE2 ; LOOP opcode.
.as:   ; Entry point for LOOPE, LOOPNE with AL=opcode.
       MOV ECX,sssWidthMask ; Detect address-size to ECX.
       AND ECX,[EDI+II.SssStatus]
       CMP DH,none ; When address-size is not overwritten by %2, use segment width in ECX.
       JE .op: ; If single operand version LOOPcc imm is used.
       ; Two-operand version LOOPxx imm, rCX is used.
       IiAbortIfNotCounter Operand2
       MOV ECX,EDX
       SHR EDX,8 ; Remove 2nd operand.
       Dispatch CL,r32,r16
       MOV ECX,sssWidth64
       JMP .op:
 .r32: MOV ECX,sssWidth32
       JMP .op:
 .r16: MOV ECX,sssWidth16
.op:   ; Common entry for LOOPcc and JrCXZ handlers.
       ; AL=opcode, ECX=address-size requested by loop counter width.
       IiEmitOpcode EAX
       IiDispatchWidth BITS32=.32:, BITS64=.64:
       ; Instruction in 16bit mode.
       JSt ECX,sssWidth16,.df:
       JSt ECX,sssWidth32,.ATOGGLE:
.E6731:IiAbort '6731' ; Required address width 64 can be used in 64bit segment only.
.E6733:IiAbort '6733' ; Required address width 16 cannot be used in 64bit segment.
   .32:JSt ECX,sssWidth32,.df:
       JSt ECX,sssWidth16,.ATOGGLE:
       JMP .E6731:
   .64:JSt ECX,sssWidth64,.df:
       JSt ECX,sssWidth16,.E6733:
.ATOGGLE:IiEmitPrefix ATOGGLE
   .df:IiAllowModifier DIST,DATA,IMM
       IiAllowPrefix HintAny, ATOGGLE
       IiDispatchFormat imm
.imm:  IiImmSize Operand1
       IiDispatchLocation [EDI+II.Operand1+EXP.Seg],NEAR=.proxy:,FAR=.proxy:
     ; Target is in the same segment, possibly in a short distance.
       IiDispatchDist NEAR=.proxy:,FAR=.proxy:,SHORT=.short: ; Use proxy jump when explicitly requested.
       IiDispatchData WORD=.proxy:,DWORD=.proxy,QWORD=.proxy:
       IiDispatchImm WORD=.proxy,DWORD=.proxy:
       Invoke IiRelocSizeRIP::,EDI,EBX ; Inspect Imm-RIP magnitude and set iiMfgIMM_Mask to EAX.
       JNSt EAX,iiMfgIMM_BYTE,.proxy: ; If the distance is above 127 bytes.
.short: ; Do not use proxy jum when explicitly requested DIST=SHORT.
       IiReloc iiRelocImmRIP
       IiEncoding DIST=SHORT,ADDR=REL,IMM=BYTE ; Standard short relative LOOP/JrCXZ.
       RET
.proxy: ; LOOP/JrCXZ to the proxy jump instead of the target.
       CALL IigJMP.imm: ; Construct the code using handler of JMP with current II object in EDI.
       DECB [EDI+II.Ppg] ; Remove opcode byte 0xE9 or 0xEA emitted by calling IigJMP.imm.
       MOV EAX,iiPpgOpcodeSizeMask
       AND EAX,[EDI+II.Ppg]
       MOV CL,[EDI+II.Opcode+EAX] ; Copy removed opcode byte 0xE9 or 0xEA to CL.
       MOV ESI,iiMfgIMM_Mask      ; Calculate size of soon-to-be-assembled JMP instruction to ESI.
       AND ESI,[EDI+II.MfgEmitted] ; Convert Imm-size to 1, 2 or 4.
       MOV EAX,[EDI+II.PfxEmitted]
       INC ESI
       JNSt EAX,iiPfxREX,.p4:
       ANDD [EDI+II.PfxEmitted],0xFFFF_FF00 ; Remove REX prefix copied to AL.
       INC ESI
  .p4: SUB EDX,EDX
       JNSt [EDI+II.PfxEmitted],iiPfxOTOGGLE, .p5:
       RstSt [EDI+II.PfxEmitted],iiPfxOTOGGLE ; Remove OTOGGLE prefix copied to DL.
       MOV DL,0x66                            ; and emit it as opcode instead.
       INC ESI
  .p5: JNSt [EDI+II.Ppg],iiPpgPara, .p6:
       ADD ESI,2
  .p6: IiEmitOpcode 0x02,0xEB,ESI ; Emit actual LOOP $+4 followed with bypassing JMPS.
       TEST EDX
       JZ .p7:
       IiEmitOpcode EDX ; Postponed OTOGGLE.
   .p7:TEST AL
       JZ .p8:
       IiEmitOpcode EAX ; Postponed REX.
   .p8:IiEmitOpcode ECX ; Postponed 0xE9 or 0xEA.
       RET ; IiFlush will arrange the actual proxy-jump target.
 ENDP IigLOOP::
↑ LOOPE
Decrement count; Jump short if count!=0 and ZF=1
Category
gen,branch,cond
Operands
eCX,Jbs | rCX,Jbs
Opcode
0xE1 | 0xE1
Flags
tested:....Z...
Tested by
t3171 t3172 t3173
IigLOOPE:: PROC
    MOV AL,0xE1
    JMP IigLOOP.as:
 ENDP IigLOOPE::
↑ LOOPZ
Decrement count; Jump short if count!=0 and ZF=1
Category
gen,branch,cond
Operands
eCX,Jbs | rCX,Jbs
Opcode
0xE1 | 0xE1
Flags
tested:....Z...
Tested by
t3171 t3172 t3173
IigLOOPZ:: PROC
    MOV AL,0xE1
    JMP IigLOOP.as:
 ENDP IigLOOPZ::
↑ LOOPNE
Decrement count; Jump short if count!=0 and ZF=0
Category
gen,branch,cond
Operands
eCX,Jbs | rCX,Jbs
Opcode
0xE0 | 0xE0
Flags
tested:....Z...
Tested by
t3171 t3172 t3173
IigLOOPNE:: PROC
    MOV AL,0xE0
    JMP IigLOOP.as:
 ENDP IigLOOPNE::
↑ LOOPNZ
Decrement count; Jump short if count!=0 and ZF=0
Category
gen,branch,cond
Operands
eCX,Jbs | rCX,Jbs
Opcode
0xE0 | 0xE0
Flags
tested:....Z...
Tested by
t3171 t3172 t3173
IigLOOPNZ:: PROC
    MOV AL,0xE0
    JMP IigLOOP.as:
 ENDP IigLOOPNZ::
↑ JCXZ
Jump short if eCX register is 0
Category
gen,branch,cond
Operands
Jbs,CX
Opcode
0xE3
Tested by
t3171 t3172
IigJCXZ:: PROC
     MOV AL,0xE3
     MOV ECX,sssWidth16
     JMP IigLOOP.op:
 ENDP IigJCXZ::
↑ JECXZ
Jump short if eCX register is 0
Category
gen,branch,cond
Operands
Jbs,ECX | Jbs,ECX
Opcode
0xE3 | 0xE3
Tested by
t3171 t3172 t3173
IigJECXZ:: PROC
     MOV AL,0xE3
     MOV ECX,sssWidth32
     JMP IigLOOP.op:
 ENDP IigJECXZ::
↑ JRCXZ
Jump short if rCX register is 0
Category
gen,branch,cond
Operands
Jbs,RCX
Opcode
0xE3
CPU
P4+
Documented
D41
Tested by
t3173
IigJRCXZ:: PROC
     MOV AL,0xE3
     MOV ECX,sssWidth64
     JMP IigLOOP.op:
 ENDP IigJRCXZ::
↑ IigJcc
IigJcc is a common handler for conditional control-transfer instructions Jcc where cc is the condition code mnemonic shortcut.
When the target distance cannot be encoded as DIST=SHORT and CPU generation is 386 or higher, it is encoded as conditional near jump.
EuroAssembler will encode near or far conditional jump Jcc Target in 16bit real mode for CPU=286 or lower as unconditional JMPN or JMPF bypassed by conditional short jump with inverted condition.
Description
Jcc
Input
CL is condition code 0x00..0x0F.
EDI is pointer to II structure with parsed operands.
EDX has operand types as set by IiAssemble.
See also
JA, JAE, JB, JBE, JC, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNLE, JNL, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ
Invokes
IiRelocSizeRIP
Tested by
t3302 t3303
IigJcc:: PROC ; CL=condition code (0..15).
       IiAllowPrefix HintAny
       IiAllowModifier DIST,DATA,IMM
       IiDispatchFormat imm, far
.imm:  IiImmSize Operand1
       Invoke IiRelocSizeRIP::,EDI,EBX ; Inspect Imm-RIP magnitude and set iiMfgIMM_Mask to EAX.
       IiDispatchLocation [EDI+II.Operand1+EXP.Seg],NEAR=.nearRel:,FAR=.proxy:
       ; Target is in the same segment, possibly in a short distance.
       IiDispatchDist NEAR=.near:,FAR=.proxy:,SHORT=.short:
       IiDispatchData DWORD=.near:,WORD=.near:,QWORD=.near:
       IiDispatchImm  DWORD=.near:,WORD=.near:
       MOV ESI,[EDI+II.Operand1+EXP.Seg] ; Target segment = current segment.
       JSt [ESI+SSS.Status],sssExtern, .nearRel:
.short: ; Direct relative short conditional jump.
       JSt EAX,iiMfgIMM_WORD|iiMfgIMM_DWORD|iiMfgIMM_QWORD,.near: ; If distance magnitude too big.
       IiEncoding DIST=SHORT,ADDR=REL,IMM=BYTE
       IiReloc iiRelocImmRIP
       OR CL,0x70
       IiEmitOpcode ECX
       IiDispatchWidth BITS64=.Q:
       RET
 .Q:   IiEncoding DATA=QWORD
       RET
.nearRel:; Standard 386 direct relative near conditional jump relocable at link time,
       ; or proxy jump bypassed by short jump with inverted condition.
       MOV ESI,iiRelocImmRel ; Relocation at link time.
       JMP .n:
.near: ; Standard 386 direct relative near conditional jump relocable at assembly time,
       MOV ESI,iiRelocImmRIP ; Relocation at assembly time.
  .n:  IiDispatchWidth BITS16=.n16:, BITS64=.n64:
       ; Near conditional jump in 32bit mode.
       IiDispatchData WORD=.oW:, DWORD=.D:
       IiDispatchImm  WORD=.oW:
  .D:  IiEncoding DATA=DWORD,IMM=DWORD,DIST=NEAR,ADDR=REL
       JMP .N:
  .oD: IiEmitPrefix OTOGGLE
       JMP .D:
 .n64: ; Near conditional jump in 64bit mode.
       IiEncoding DATA=QWORD,IMM=DWORD,DIST=NEAR,ADDR=REL
  .N:  IiReloc ESI ; Request for relocation iiRelocImmRIP or iiRelocImmRel.
       OR CL,0x80 ; Standard 386 near conditional jump.
       IiEmitOpcode 0x0F,ECX
       RET
 .n16: ; Near conditional jump in 16bit mode.
       JNSt [Ea.Eaopt::+EAOPT.Machine],iiCPU_386, .proxy: ; If CPU older than 386.
       JSt EAX,iiMfgIMM_DWORD|iiMfgIMM_QWORD,.oD:
       IiDispatchData DWORD=.oD:, WORD=.W:
       IiDispatchImm  DWORD=.oD:
  .W:  IiEncoding DATA=WORD,IMM=WORD,DIST=NEAR,ADDR=REL
       JMP .N:
 .oW:  IiEmitPrefix OTOGGLE
       JMP .W:
.far:
.proxy: ; Bypass unconditional JMP by short conditional jump with inverted condition CL.
       XOR CL,1 ; Invert condition code.
       OR CL,0x70
       IiEmitOpcode ECX
       CALL IigJMP.imm:  ; Hire unconditional JMP handler to emit near or far jump.
       DECB [EDI+II.Ppg] ; Remove opcode byte 0xE9 or 0xEA emitted by calling IigJMP.imm.
       MOV EAX,iiPpgOpcodeSizeMask
       AND EAX,[EDI+II.Ppg]
       MOV CL,[EDI+II.Opcode+EAX]  ; Copy removed opcode byte 0xE9 or 0xEA to CL.
       MOV ESI,iiMfgIMM_Mask       ; Calculate size of soon-to-be-assembled JMP instruction to ESI.
       AND ESI,[EDI+II.MfgEmitted] ; Convert Imm-size to 1, 2 or 4.
       MOV EAX,[EDI+II.PfxEmitted]
       INC ESI
       JNSt EAX,iiPfxREX,.p4:
       ANDD [EDI+II.PfxEmitted],0xFFFF_FF00 ; Remove REX prefix which was just copied to AL.
       INC ESI
  .p4: SUB EDX,EDX
       JNSt [EDI+II.PfxEmitted],iiPfxOTOGGLE, .p5:
       RstSt [EDI+II.PfxEmitted],iiPfxOTOGGLE ; Remove OTOGGLE prefix copied to DL.
       MOV DL,0x66
       INC ESI
  .p5: JNSt [EDI+II.Ppg],iiPpgPara, .p6:
       ADD ESI,2
  .p6: IiEmitOpcode ESI ; Bypassing JMPS value of cb.
       TEST EDX
       JZ .p7:
       IiEmitOpcode EDX ; Postponed OTOGGLE.
   .p7:TEST AL
       JZ .p8:
       IiEmitOpcode EAX ; Postponed REX.
   .p8:IiEmitOpcode ECX ; Postponed JMP opcode 0xE9 or 0xEA.
       RET
    ENDP IigJcc::
↑ JA
Jump short if not below or equal/above (CF=0 AND ZF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x77 ^tTTN | 0x0F87 ^tTTN
Flags
tested:....Z..C
IigJA:: PROC
    MOV CL,0111b
    JMP IigJcc:
 ENDP IigJA::
↑ JAE
Jump short if not below/above or equal/not carry (CF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x73 ^ttTN | 0x0F83 ^ttTN
Flags
tested:.......C
IigJAE:: PROC
    MOV CL,0011b
    JMP IigJcc:
 ENDP IigJAE::
↑ JB
Jump short if below/not above or equal/carry (CF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x72 ^ttTn | 0x0F82 ^ttTn
Flags
tested:.......C
IigJB:: PROC
    MOV CL,0010b
    JMP IigJcc:
 ENDP IigJB::
↑ JBE
Jump short if below or equal/not above (CF=1 AND ZF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x76 ^tTTn | 0x0F86 ^tTTn
Flags
tested:....Z..C
IigJBE:: PROC
    MOV CL,0110b
    JMP IigJcc:
 ENDP IigJBE::
↑ JC
Jump short if below/not above or equal/carry (CF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x72 ^ttTn | 0x0F82 ^ttTn
Flags
tested:.......C
IigJC:: PROC
    MOV CL,0010b
    JMP IigJcc:
 ENDP IigJC::
↑ JE
Jump short if zero/equal (ZF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x74 ^tTtn | 0x0F84 ^tTtn
Flags
tested:....Z...
IigJE:: PROC
    MOV CL,0100b
    JMP IigJcc:
 ENDP IigJE::
↑ JG
Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7F ^TTTN | 0x0F8F ^TTTN
Flags
tested:O..SZ...
IigJG:: PROC
    MOV CL,1111b
    JMP IigJcc:
 ENDP IigJG::
↑ JGE
Jump short if not less/greater or equal (SF=OF)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7D ^TTtN | 0x0F8D ^TTtN
Flags
tested:O..S....
IigJGE:: PROC
    MOV CL,1101b
    JMP IigJcc:
 ENDP IigJGE::
↑ JL
Jump short if less/not greater (SF!=OF)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7C ^TTtn | 0x0F8C ^TTtn
Flags
tested:O..S....
IigJL:: PROC
    MOV CL,1100b
    JMP IigJcc:
 ENDP IigJL::
↑ JLE
Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7E ^TTTn | 0x0F8E ^TTTn
Flags
tested:O..SZ...
IigJLE:: PROC
    MOV CL,1110b
    JMP IigJcc:
 ENDP IigJLE::
↑ JNA
Jump short if below or equal/not above (CF=1 AND ZF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x76 ^tTTn | 0x0F86 ^tTTn
Flags
tested:....Z..C
IigJNA:: PROC
    MOV CL,0110b
    JMP IigJcc:
 ENDP IigJNA::
↑ JNAE
Jump short if below/not above or equal/carry (CF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x72 ^ttTn | 0x0F82 ^ttTn
Flags
tested:.......C
IigJNAE:: PROC
    MOV CL,0010b
    JMP IigJcc:
 ENDP IigJNAE::
↑ JNB
Jump short if not below/above or equal/not carry (CF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x73 ^ttTN | 0x0F83 ^ttTN
Flags
tested:.......C
IigJNB:: PROC
    MOV CL,0011b
    JMP IigJcc:
 ENDP IigJNB::
↑ JNBE
Jump short if not below or equal/above (CF=0 AND ZF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x77 ^tTTN | 0x0F87 ^tTTN
Flags
tested:....Z..C
IigJNBE:: PROC
    MOV CL,0111b
    JMP IigJcc:
 ENDP IigJNBE::
↑ JNC
Jump short if not below/above or equal/not carry (CF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x73 ^ttTN | 0x0F83 ^ttTN
Flags
tested:.......C
IigJNC:: PROC
    MOV CL,0011b
    JMP IigJcc:
 ENDP IigJNC::
↑ JNE
Jump short if not zero/not equal (ZF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x75 ^tTtN | 0x0F85 ^tTtN
Flags
tested:....Z...
IigJNE:: PROC
    MOV CL,0101b
    JMP IigJcc:
 ENDP IigJNE::
↑ JNG
Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7E ^TTTn | 0x0F8E ^TTTn
Flags
tested:O..SZ...
IigJNG:: PROC
    MOV CL,1110b
    JMP IigJcc:
 ENDP IigJNG::
↑ JNGE
Jump short if less/not greater (SF!=OF)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7C ^TTtn | 0x0F8C ^TTtn
Flags
tested:O..S....
IigJNGE:: PROC
    MOV CL,1100b
    JMP IigJcc:
 ENDP IigJNGE::
↑ JNL
Jump short if not less/greater or equal (SF=OF)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7D ^TTtN | 0x0F8D ^TTtN
Flags
tested:O..S....
IigJNL:: PROC
    MOV CL,1101b
    JMP IigJcc:
 ENDP IigJNL::
↑ JNLE
Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7F ^TTTN | 0x0F8F ^TTTN
Flags
tested:O..SZ...
IigJNLE:: PROC
    MOV CL,1111b
    JMP IigJcc:
 ENDP IigJNLE::
↑ JNO
Jump short if not overflow (OF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x71 ^tttN | 0x0F81 ^tttN
Flags
tested:O.......
IigJNO:: PROC
    MOV CL,0001b
    JMP IigJcc:
 ENDP IigJNO::
↑ JNP
Jump short if not parity/parity odd
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7B ^TtTN | 0x0F8B ^TtTN
Flags
tested:......P.
IigJNP:: PROC
    MOV CL,1011b
    JMP IigJcc:
 ENDP IigJNP::
↑ JNS
Jump short if not sign (SF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x79 ^TttN | 0x0F89 ^TttN
Flags
tested:...S....
IigJNS:: PROC
    MOV CL,1001b
    JMP IigJcc:
 ENDP IigJNS::
↑ JNZ
Jump short if not zero/not equal (ZF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x75 ^tTtN | 0x0F85 ^tTtN
Flags
tested:....Z...
IigJNZ:: PROC
    MOV CL,0101b
    JMP IigJcc:
 ENDP IigJNZ::
↑ JO
Jump short if overflow (OF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x70 ^tttn | 0x0F80 ^tttn
Flags
tested:O.......
Tested by
t3301
IigJO:: PROC
    MOV CL,0000b
    JMP IigJcc:
 ENDP IigJO::
↑ JP
Jump short if parity/parity even (PF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7A ^TtTn | 0x0F8A ^TtTn
Flags
tested:......P.
IigJP:: PROC
    MOV CL,1010b
    JMP IigJcc:
 ENDP IigJP::
↑ JPE
Jump short if parity/parity even (PF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7A ^TtTn | 0x0F8A ^TtTn
Flags
tested:......P.
IigJPE:: PROC
    MOV CL,1010b
    JMP IigJcc:
 ENDP IigJPE::
↑ JPO
Jump short if not parity/parity odd
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x7B ^TtTN | 0x0F8B ^TtTN
Flags
tested:......P.
IigJPO:: PROC
    MOV CL,1011b
    JMP IigJcc:
 ENDP IigJPO::
↑ JS
Jump short if sign (SF=1)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x78 ^Tttn | 0x0F88 ^Tttn
Flags
tested:...S....
IigJS:: PROC
    MOV CL,1000b
    JMP IigJcc:
 ENDP IigJS::
↑ JZ
Jump short if zero/equal (ZF=0)
Category
gen,branch,cond
Operands
Jbs | Jvds
Opcode
0x74 ^tTtn | 0x0F84 ^tTtn
Flags
tested:....Z...
IigJZ:: PROC
    MOV CL,0100b
    JMP IigJcc:
 ENDP IigJZ::
↑ RET
Return from procedure
Description
RET
Category
gen,branch stack
Operands
Iw |
Opcode
0xC2 | 0xC3 | 0xCA | 0xCB
Tested by
t3321
Invokes
CtxPeek
IigRET:: PROC
      IiAllowModifier CODE,DIST,DATA,IMM
      SUB EAX,EAX
      IiDispatchFormat none,imm
.imm: CMPD [EDI+II.Operand1+EXP.Low],EAX
      JNZ .iw: ; If operand nonzero.
.none:IiDispatchImm   WORD=.iw:
      IiDispatchCode SHORT=.iw:
      IiEncoding CODE=LONG ; Without immediate operand.
      MOV CX,0xC3CB ; Opcode RETN in CH, RETF in CL.
      JMP .dist:
.iw:  IiEncoding CODE=SHORT,IMM=WORD
      MOV CX,0xC2CA ; Opcode RETN imm in CH, RETF imm in CL.
      IiEmitImm Operand1, WORD
.dist:IiDispatchDist NEAR=.near:, FAR=.far: ; Decide the distance by explicit suffix or DIST= modifier.
      Invoke CtxPeek::, ctxPROC | ctxPROC1, EAX ; If no explicit specification, use PROC(1) property DIST=.
      JC .near:  ; If not in PROC context, default to NEAR.
      MOV EDX,[EAX+CTX.ObjPtr] ; Get pointer to the symbol of procedure where this RET lies is.
      JSt [EDX+SYM.Status],symFar, .far:
.near:IiEncoding DIST=NEAR
      SHR ECX,8
      IiEmitOpcode ECX
      JMP .w:
.far: IiEncoding DIST=FAR ; Either explicit RETF or RET inside PROC DIST=FAR block.
      IiEmitOpcode ECX
 .w:  IiDispatchWidth BITS16=.16:, BITS32=.32:
      JSt [EDI+II.MfgEmitted],iiMfgDIST_NEAR, .n64: ; If encoding DIST=NEAR in 64bit mode.
      IiDispatchData DWORD=.dD:, WORD=.dOW:         ; If encoding DIST=FAR  in 64bit mode.
      IiEmitPrefix REX.W ; Promote RETF in 64bit mode.
 .dQ: IiEncoding DATA=QWORD
      RET
 .n64:IiDispatchData WORD=.dOW:
      JMP .dQ:
 .16: IiDispatchData DWORD=.dOD:
 .dW: IiEncoding DATA=WORD
      RET
 .32: IiDispatchData WORD=.dOW:
 .dD: IiEncoding DATA=DWORD
      RET
 .dOD:IiEmitPrefix OTOGGLE
      JMP .dD:
 .dOW:IiEmitPrefix OTOGGLE
      JMP .dW:
 ENDP IigRET::
↑ RETN
Return from NEAR procedure
Category
gen,branch stack
Operands
Iw |
Opcode
0xC2 | 0xC3
Tested by
t3321
IigRETN:: PROC
    IiSuffixed RET,N
 ENDP IigRETN::
↑ RETF
Return from FAR procedure
Category
gen,branch stack
Operands
Iw |
Opcode
0xCA | 0xCB
Tested by
t3321
IigRETF:: PROC
    IiSuffixed RET,F
 ENDP IigRETF::
↑ IRET
Interrupt Return
Description
IRET
Category
gen,break stack
Operands
Fwo | Fwo
Opcode
0xCF | 0xCF
Tested by
t3321
IigIRET:: PROC
      IiAllowModifier DATA
      IiEmitOpcode 0xCF
      IiDispatchFormat none
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiDispatchData DWORD=.oD:
 .W:  IiEncoding DIST=FAR,DATA=WORD
      RET
 .oW: IiEmitPrefix OTOGGLE
      JMP .W:
 .32: IiDispatchData WORD=.oW:
 .D:  IiEncoding DIST=FAR,DATA=DWORD
      RET
 .oD: IiEmitPrefix OTOGGLE
      JMP .D:
.64:  IiDispatchData WORD=.oW:, DWORD=.D:
      IiEmitPrefix REX.W
      IiEncoding DIST=FAR,DATA=QWORD
      RET
 ENDP IigIRET::
↑ IRETW
Interrupt Return, operand-size WORD
Category
gen,break stack
Operands
Fdo | Fdo
Opcode
0xCF
Tested by
t3321
IigIRETW:: PROC
    IiSuffixed IRET,W
 ENDP IigIRETW::
↑ IRETD
Interrupt Return, operand-size DWORD
Description
IRETD
Category
gen,break stack
Operands
Fdo | Fdo
Opcode
0xCF
Tested by
t3321
IigIRETD:: PROC
    IiSuffixed IRET,D
 ENDP IigIRETD::
↑ IRETQ
Interrupt Return, operand-size QWORD
Category
gen,break stack
Operands
Fqp
Opcode
0xCF
Tested by
t3321
IigIRETQ:: PROC
    IiSuffixed IRET,Q
 ENDP IigIRETQ::
↑ INT
Call to Interrupt Procedure
Category
gen,break stack
Operands
Ib,Fv
Opcode
0xCD
Flags
modified:..I....., defined:..I....., values:..I.....
Tested by
t3325
IigINT:: PROC
    IiAllowModifier IMM
    IiEmitOpcode 0xCD
    IiEmitImm Operand1,BYTE
    IiDispatchFormat imm
.imm:RET
 ENDP IigINT::
↑ INT1
Call to Interrupt Procedure
Category
gen,break stack
Operands
Fv
Opcode
0xF1
Flags
modified:..I....., defined:..I....., values:..I.....
CPU
03+
Documented
U17
Tested by
t3325
IigINT1:: PROC
    IiRequire 386,UNDOC
    IiEmitOpcode 0xF1
    IiDispatchFormat none
.none:RET
 ENDP IigINT1::
↑ SMI
System Management Interrupt
Operands
-
Opcode
0xF1
CPU
386 AMD
Tested by
t3325
IigSMI:: PROC
    IiRequire AMD
    JMP IigINT1:
 ENDP IigSMI::
↑ INT3
Breakpoint INT 3 call
Tested by
t3325
IigINT3:: PROC
      IiDispatchFormat none
.none:IiEmitOpcode 0xCC
      RET
 ENDP IigINT3::
↑ INTO
Overflow INT 4 call
Description
INTO
Category
gen,break stack
Operands
Fv
Opcode
0xCE
Flags
tested:O......., modified:..I....., defined:..I....., values:..I.....
Tested by
t3325
IigINTO:: PROC
      IiAbortIf64
      IiEmitOpcode 0xCE
      IiDispatchFormat none
.none:RET
 ENDP IigINTO::
↑ SETcc
Set Byte on Condition
Description
SETcc
Category
gen,datamov
Operands
Eb
Opcode
0x0F9c /0
Input
AL=condition code 0..15.
CPU
03+
Documented
D33
Tested by
t3311
See also
SETA, SETAE, SETB, SETBE, SETC, SETE, SETG, SETGE, SETL, SETLE, SETNA, SETNAE, SETNB, SETNBE, SETNC, SETNE, SETNG, SETNGE, SETNLE, SETNL, SETNO, SETNP, SETNS, SETNZ, SETO, SETP, SETPE, SETPO, SETS, SETZ
IigSETcc:: PROC
     IiRequire 386
     IiDataSize BYTE
     OR AL,0x90
     IiEmitOpcode 0x0F,EAX
     IiOpEn  M
     IiModRM /0
     IiDispatchFormat r8:,m8
.r8:
.m8: RET
    ENDP IigSETcc::
↑ SETA
Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F97 ^tTTN /0
Flags
tested:....Z..C
CPU
03+
Documented
D33
IigSETA:: PROC
    MOV AL,0111b
    JMP IigSETcc:
 ENDP IigSETA::
↑ SETAE
Set Byte on Condition - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F93 ^ttTN /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETAE:: PROC
    MOV AL,0011b
    JMP IigSETcc:
 ENDP IigSETAE::
↑ SETB
Set Byte on Condition - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F92 ^ttTn /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETB:: PROC
    MOV AL,0010b
    JMP IigSETcc:
 ENDP IigSETB::
↑ SETBE
Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F96 ^tTTn /0
Flags
tested:....Z..C
CPU
03+
Documented
D33
IigSETBE:: PROC
    MOV AL,0110b
    JMP IigSETcc:
 ENDP IigSETBE::
↑ SETC
Set Byte on Condition - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F92 ^ttTn /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETC:: PROC
    MOV AL,0010b
    JMP IigSETcc:
 ENDP IigSETC::
↑ SETE
Set Byte on Condition - zero/equal (ZF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F94 ^tTtn /0
Flags
tested:....Z...
CPU
03+
Documented
D33
IigSETE:: PROC
    MOV AL,0100b
    JMP IigSETcc:
 ENDP IigSETE::
↑ SETG
Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,datamov
Operands
Eb
Opcode
0x0F9F ^TTTN /0
Flags
tested:O..SZ...
CPU
03+
Documented
D33
IigSETG:: PROC
    MOV AL,1111b
    JMP IigSETcc:
 ENDP IigSETG::
↑ SETGE
Set Byte on Condition - not less/greater or equal (SF=OF)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9D ^TTtN /0
Flags
tested:O..S....
CPU
03+
Documented
D33
IigSETGE:: PROC
    MOV AL,1101b
    JMP IigSETcc:
 ENDP IigSETGE::
↑ SETL
Set Byte on Condition - less/not greater (SF!=OF)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9C ^TTtn /0
Flags
tested:O..S....
CPU
03+
Documented
D33
IigSETL:: PROC
    MOV AL,1100b
    JMP IigSETcc:
 ENDP IigSETL::
↑ SETLE
Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,datamov
Operands
Eb
Opcode
0x0F9E ^TTTn /0
Flags
tested:O..SZ...
CPU
03+
Documented
D33
IigSETLE:: PROC
    MOV AL,1110b
    JMP IigSETcc:
 ENDP IigSETLE::
↑ SETNA
Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F96 ^tTTn /0
Flags
tested:....Z..C
CPU
03+
Documented
D33
IigSETNA:: PROC
    MOV AL,0110b
    JMP IigSETcc:
 ENDP IigSETNA::
↑ SETNAE
Set Byte on Condition - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F92 ^ttTn /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETNAE:: PROC
    MOV AL,0010b
    JMP IigSETcc:
 ENDP IigSETNAE::
↑ SETNB
Set Byte on Condition - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F93 ^ttTN /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETNB:: PROC
    MOV AL,0011b
    JMP IigSETcc:
 ENDP IigSETNB::
↑ SETNBE
Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F97 ^tTTN /0
Flags
tested:....Z..C
CPU
03+
Documented
D33
IigSETNBE:: PROC
    MOV AL,0111b
    JMP IigSETcc:
 ENDP IigSETNBE::
↑ SETNC
Set Byte on Condition - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F93 ^ttTN /0
Flags
tested:.......C
CPU
03+
Documented
D33
IigSETNC:: PROC
    MOV AL,0011b
    JMP IigSETcc:
 ENDP IigSETNC::
↑ SETNE
Set Byte on Condition - not zero/not equal (ZF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F95 ^tTtN /0
Flags
tested:....Z...
CPU
03+
Documented
D33
IigSETNE:: PROC
    MOV AL,0101b
    JMP IigSETcc:
 ENDP IigSETNE::
↑ SETNG
Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,datamov
Operands
Eb
Opcode
0x0F9E ^TTTn /0
Flags
tested:O..SZ...
CPU
03+
Documented
D33
IigSETNG:: PROC
    MOV AL,1110b
    JMP IigSETcc:
 ENDP IigSETNG::
↑ SETNGE
Set Byte on Condition - less/not greater (SF!=OF)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9C ^TTtn /0
Flags
tested:O..S....
CPU
03+
Documented
D33
IigSETNGE:: PROC
    MOV AL,1100b
    JMP IigSETcc:
 ENDP IigSETNGE::
↑ SETNL
Set Byte on Condition - not less/greater or equal (SF=OF)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9D ^TTtN /0
Flags
tested:O..S....
CPU
03+
Documented
D33
IigSETNL:: PROC
    MOV AL,1101b
    JMP IigSETcc:
 ENDP IigSETNL::
↑ SETNLE
Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,datamov
Operands
Eb
Opcode
0x0F9F ^TTTN /0
Flags
tested:O..SZ...
CPU
03+
Documented
D33
IigSETNLE:: PROC
    MOV AL,1111b
    JMP IigSETcc:
 ENDP IigSETNLE::
↑ SETNO
Set Byte on Condition - not overflow (OF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F91 ^tttN /0
Flags
tested:O.......
CPU
03+
Documented
D33
IigSETNO:: PROC
    MOV AL,0001b
    JMP IigSETcc:
 ENDP IigSETNO::
↑ SETNP
Set Byte on Condition - not parity/parity odd
Category
gen,datamov
Operands
Eb
Opcode
0x0F9B ^TtTN /0
Flags
tested:......P.
CPU
03+
Documented
D33
IigSETNP:: PROC
    MOV AL,1011b
    JMP IigSETcc:
 ENDP IigSETNP::
↑ SETNS
Set Byte on Condition - not sign (SF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F99 ^TttN /0
Flags
tested:...S....
CPU
03+
Documented
D33
IigSETNS:: PROC
    MOV AL,1001b
    JMP IigSETcc:
 ENDP IigSETNS::
↑ SETNZ
Set Byte on Condition - not zero/not equal (ZF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F95 ^tTtN /0
Flags
tested:....Z...
CPU
03+
Documented
D33
IigSETNZ:: PROC
    MOV AL,0101b
    JMP IigSETcc:
 ENDP IigSETNZ::
↑ SETO
Set Byte on Condition - overflow (OF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F90 ^tttn /0
Flags
tested:O.......
CPU
03+
Documented
D33
IigSETO:: PROC
    MOV AL,0000b
    JMP IigSETcc:
 ENDP IigSETO::
↑ SETP
Set Byte on Condition - parity/parity even (PF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9A ^TtTn /0
Flags
tested:......P.
CPU
03+
Documented
D33
IigSETP:: PROC
    MOV AL,1010b
    JMP IigSETcc:
 ENDP IigSETP::
↑ SETPE
Set Byte on Condition - parity/parity even (PF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F9A ^TtTn /0
Flags
tested:......P.
CPU
03+
Documented
D33
IigSETPE:: PROC
    MOV AL,1010b
    JMP IigSETcc:
 ENDP IigSETPE::
↑ SETPO
Set Byte on Condition - not parity/parity odd
Category
gen,datamov
Operands
Eb
Opcode
0x0F9B ^TtTN /0
Flags
tested:......P.
CPU
03+
Documented
D33
IigSETPO:: PROC
    MOV AL,1011b
    JMP IigSETcc:
 ENDP IigSETPO::
↑ SETS
Set Byte on Condition - sign (SF=1)
Category
gen,datamov
Operands
Eb
Opcode
0x0F98 ^Tttn /0
Flags
tested:...S....
CPU
03+
Documented
D33
IigSETS:: PROC
    MOV AL,1000b
    JMP IigSETcc:
 ENDP IigSETS::
↑ SETZ
Set Byte on Condition - zero/equal (ZF=0)
Category
gen,datamov
Operands
Eb
Opcode
0x0F94 ^tTtn /0
Flags
tested:....Z...
CPU
03+
Documented
D33
IigSETZ:: PROC
    MOV AL,0100b
    JMP IigSETcc:
 ENDP IigSETZ::
↑ CMOVcc
Conditional Move
Description
CMOVcc
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4c /r
Input
AL=condition code 0..15.
Flags
tested:....Z..C
CPU
PP+
Documented
D32
Tested by
t3315
See also
CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNLE, CMOVNL, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ
IigCMOVcc:: PROC
     IiRequire 686
     OR AL,0x40
     IiEmitOpcode 0x0F,EAX
     IiOpEn RM
     IiModRM /r
     IiDataSize
     IiDispatchFormat r16.r16, r16.m16, r32.r32, r32.m32, r64.r64, r64.m64
.r16.r16:
.r16.m16:
.r32.r32:
.r32.m32:
.r64.r64:
.r64.m64:
     RET
    ENDP IigCMOVcc::
↑ CMOVA
Conditional Move - not below or equal/above (CF=0 AND ZF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F47 ^tTTN /r
Flags
tested:....Z..C
CPU
PP+
Documented
D32
IigCMOVA:: PROC
    MOV AL,0111b
    JMP IigCMOVcc:
 ENDP IigCMOVA::
↑ CMOVAE
Conditional Move - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F43 ^ttTN /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVAE:: PROC
    MOV AL,0011b
    JMP IigCMOVcc:
 ENDP IigCMOVAE::
↑ CMOVB
Conditional Move - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F42 ^ttTn /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVB:: PROC
    MOV AL,0010b
    JMP IigCMOVcc:
 ENDP IigCMOVB::
↑ CMOVBE
Conditional Move - below or equal/not above (CF=1 AND ZF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F46 ^tTTn /r
Flags
tested:....Z..C
CPU
PP+
Documented
D32
IigCMOVBE:: PROC
    MOV AL,0110b
    JMP IigCMOVcc:
 ENDP IigCMOVBE::
↑ CMOVC
Conditional Move - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F42 ^ttTn /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVC:: PROC
    MOV AL,0010b
    JMP IigCMOVcc:
 ENDP IigCMOVC::
↑ CMOVE
Conditional Move - zero/equal (ZF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F44 ^tTtn /r
Flags
tested:....Z...
CPU
PP+
Documented
D32
IigCMOVE:: PROC
    MOV AL,0100b
    JMP IigCMOVcc:
 ENDP IigCMOVE::
↑ CMOVG
Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4F ^TTTN /r
Flags
tested:O..SZ...
CPU
PP+
Documented
D32
IigCMOVG:: PROC
    MOV AL,1111b
    JMP IigCMOVcc:
 ENDP IigCMOVG::
↑ CMOVGE
Conditional Move - not less/greater or equal (SF=OF)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4D ^TTtN /r
Flags
tested:O..S....
CPU
PP+
Documented
D32
IigCMOVGE:: PROC
    MOV AL,1101b
    JMP IigCMOVcc:
 ENDP IigCMOVGE::
↑ CMOVL
Conditional Move - less/not greater (SF!=OF)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4C ^TTtn /r
Flags
tested:O..S....
CPU
PP+
Documented
D32
IigCMOVL:: PROC
    MOV AL,1100b
    JMP IigCMOVcc:
 ENDP IigCMOVL::
↑ CMOVLE
Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4E ^TTTn /r
Flags
tested:O..SZ...
CPU
PP+
Documented
D32
IigCMOVLE:: PROC
    MOV AL,1110b
    JMP IigCMOVcc:
 ENDP IigCMOVLE::
↑ CMOVNA
Conditional Move - below or equal/not above (CF=1 AND ZF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F46 ^tTTn /r
Flags
tested:....Z..C
CPU
PP+
Documented
D32
IigCMOVNA:: PROC
    MOV AL,0110b
    JMP IigCMOVcc:
 ENDP IigCMOVNA::
↑ CMOVNAE
Conditional Move - below/not above or equal/carry (CF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F42 ^ttTn /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVNAE:: PROC
    MOV AL,0010b
    JMP IigCMOVcc:
 ENDP IigCMOVNAE::
↑ CMOVNB
Conditional Move - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F43 ^ttTN /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVNB:: PROC
    MOV AL,0011b
    JMP IigCMOVcc:
 ENDP IigCMOVNB::
↑ CMOVNBE
Conditional Move - not below or equal/above (CF=0 AND ZF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F47 ^tTTN /r
Flags
tested:....Z..C
CPU
PP+
Documented
D32
IigCMOVNBE:: PROC
    MOV AL,0111b
    JMP IigCMOVcc:
 ENDP IigCMOVNBE::
↑ CMOVNC
Conditional Move - not below/above or equal/not carry (CF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F43 ^ttTN /r
Flags
tested:.......C
CPU
PP+
Documented
D32
IigCMOVNC:: PROC
    MOV AL,0011b
    JMP IigCMOVcc:
 ENDP IigCMOVNC::
↑ CMOVNE
Conditional Move - not zero/not equal (ZF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F45 ^tTtN /r
Flags
tested:....Z...
CPU
PP+
Documented
D32
IigCMOVNE:: PROC
    MOV AL,0101b
    JMP IigCMOVcc:
 ENDP IigCMOVNE::
↑ CMOVNG
Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4E ^TTTn /r
Flags
tested:O..SZ...
CPU
PP+
Documented
D32
IigCMOVNG:: PROC
    MOV AL,1110b
    JMP IigCMOVcc:
 ENDP IigCMOVNG::
↑ CMOVNGE
Conditional Move - less/not greater (SF!=OF)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4C ^TTtn /r
Flags
tested:O..S....
CPU
PP+
Documented
D32
IigCMOVNGE:: PROC
    MOV AL,1100b
    JMP IigCMOVcc:
 ENDP IigCMOVNGE::
↑ CMOVNL
Conditional Move - not less/greater or equal (SF=OF)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4D ^TTtN /r
Flags
tested:O..S....
CPU
PP+
Documented
D32
IigCMOVNL:: PROC
    MOV AL,1101b
    JMP IigCMOVcc:
 ENDP IigCMOVNL::
↑ CMOVNLE
Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4F ^TTTN /r
Flags
tested:O..SZ...
CPU
PP+
Documented
D32
IigCMOVNLE:: PROC
    MOV AL,1111b
    JMP IigCMOVcc:
 ENDP IigCMOVNLE::
↑ CMOVNO
Conditional Move - not overflow (OF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F41 ^tttN /r
Flags
tested:O.......
CPU
PP+
Documented
D32
IigCMOVNO:: PROC
    MOV AL,0001b
    JMP IigCMOVcc:
 ENDP IigCMOVNO::
↑ CMOVNP
Conditional Move - not parity/parity odd
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4B ^TtTN /r
Flags
tested:......P.
CPU
PP+
Documented
D32
IigCMOVNP:: PROC
    MOV AL,1011b
    JMP IigCMOVcc:
 ENDP IigCMOVNP::
↑ CMOVNS
Conditional Move - not sign (SF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F49 ^TttN /r
Flags
tested:...S....
CPU
PP+
Documented
D32
IigCMOVNS:: PROC
    MOV AL,1001b
    JMP IigCMOVcc:
 ENDP IigCMOVNS::
↑ CMOVNZ
Conditional Move - not zero/not equal (ZF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F45 ^tTtN /r
Flags
tested:....Z...
CPU
PP+
Documented
D32
IigCMOVNZ:: PROC
    MOV AL,0101b
    JMP IigCMOVcc:
 ENDP IigCMOVNZ::
↑ CMOVO
Conditional Move - overflow (OF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F40 ^tttn /r
Flags
tested:O.......
CPU
PP+
Documented
D32
IigCMOVO:: PROC
    MOV AL,0000b
    JMP IigCMOVcc:
 ENDP IigCMOVO::
↑ CMOVP
Conditional Move - parity/parity even (PF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4A ^TtTn /r
Flags
tested:......P.
CPU
PP+
Documented
D32
IigCMOVP:: PROC
    MOV AL,1010b
    JMP IigCMOVcc:
 ENDP IigCMOVP::
↑ CMOVPE
Conditional Move - parity/parity even (PF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4A ^TtTn /r
Flags
tested:......P.
CPU
PP+
Documented
D32
IigCMOVPE:: PROC
    MOV AL,1010b
    JMP IigCMOVcc:
 ENDP IigCMOVPE::
↑ CMOVPO
Conditional Move - not parity/parity odd
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F4B ^TtTN /r
Flags
tested:......P.
CPU
PP+
Documented
D32
IigCMOVPO:: PROC
    MOV AL,1011b
    JMP IigCMOVcc:
 ENDP IigCMOVPO::
↑ CMOVS
Conditional Move - sign (SF=1)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F48 ^Tttn /r
Flags
tested:...S....
CPU
PP+
Documented
D32
IigCMOVS:: PROC
    MOV AL,1000b
    JMP IigCMOVcc:
 ENDP IigCMOVS::
↑ CMOVZ
Conditional Move - zero/equal (ZF=0)
Category
gen,datamov
Operands
Gvqp,Evqp
Opcode
0x0F44 ^tTtn /r
Flags
tested:....Z...
CPU
PP+
Documented
D32
IigCMOVZ:: PROC
    MOV AL,0100b
    JMP IigCMOVcc:
 ENDP IigCMOVZ::
↑ XCHG
Exchange Register/Memory with Register
Description
XCHG
Category
gen,datamov
Operands
Gb,Eb | Gvqp,Evqp | Zvqp,rAX
Opcode
0x86 ^Dw /r | 0x87 ^DW /r | 0x90 ^+r
Tested by
t3202
IigXCHG:: PROC
    IiAllowLocking Operand1,Operand2
    IiAllowModifier CODE
    IiDataSize 
    IiDispatchFormat r8.r8, r8.m8, m8.r8, r16.r16, r16.m16, m16.r16, \
                     r32.r32, r32.m32, m32.r32, r64.r64, r64.m64, m64.r64
.m8.r8:IiEncoding DATA=BYTE,CODE=LONG
    IiEmitOpcode 0x86
    IiOpEn MR
    IiModRM /r
    RET
.r8.r8:IiDispatchCode LONG=.m8.r8:
.r8.m8:IiEncoding DATA=BYTE,CODE=SHORT
    IiEmitOpcode 0x86
    IiOpEn RM
    IiModRM /r
    RET
.m64.r64:    
.m32.r32:    
.m16.r16:IiEncoding DATA=WORD,CODE=LONG
    IiEmitOpcode 0x87
    IiOpEn MR
    IiModRM /r
    RET
.r64.m64:    
.r32.m32:    
.r16.m16:IiEncoding DATA=WORD,CODE=SHORT
    IiEmitOpcode 0x87
    IiOpEn RM
    IiModRM /r
    RET  
.r64.r64:    
.r32.r32:      
.r16.r16:
    IiDispatchCode LONG=.m16.r16:
    MOV EAX,[EDI+II.Operand2+EXP.Low]
    IiDispatchNotAccum Operand1, .20:
.10:IiEncoding DATA=WORD,CODE=SHORT
    AND AL,iiReg_Ord8
    OR AL,0x90
    IiEmitOpcode EAX
    RET
.20:MOV EAX,[EDI+II.Operand1+EXP.Low]
    IiDispatchNotAccum Operand2, .r16.m16:
    JMP .10:  
 ENDP IigXCHG::
↑ XLAT
Table Look-up Translation
Description
XLAT
Category
gen,datamov
Operands
AL,BBb
Opcode
0xD7
Tested by
t3203
IigXLAT:: PROC
      IiAllowPrefix SegAny
      IiAllowModifier DATA
      IiEncoding DATA=BYTE
      IiEmitOpcode 0xD7
      IiDispatchFormat none, mem
.mem: MOV ECX,[EDI+II.Operand1+EXP.Status]
      TEST ECX,expScale|expIndex|expScalePres|expIndexPres|expDwidth
.E7541:Msg cc=NZ,'7541' ; XLAT accepts operand in the form [segment:rBX] only.
      JNSt ECX,expSegmPres, .10:
      MOV EAX,expSegm
      AND EAX,ECX
      SHR EAX,24 ; EAX is now Sreg ordinal 0..5.
      CMP AL,3
      JE .10: ; Omit segment override when DS requested.
      ADD AL,20 ; EAX is now 20..25, i.e. iiPfxSEGES..iiPfxSEGGS.
      BTS [EDI+II.PfxEmitted],EAX ; Request for segment override.
  .10:JNSt ECX,expBasePres,.none:
      AND ECX,expBase
      CMP ECX,0x00030000 ; BX,EBX,RBX.
      JNE .E7541:
      MOV ECX,[EDI+II.Operand1+EXP.Status] ; Expression address-size in bits 30,31.
      SHR ECX,30 ; ECX is now 0,1,2,3 when basereg was Unknown, BX, EBX, RBX.
      IiDispatchWidth BITS32=.32:, BITS64=.64:
      CMP CL,2
      JB .none:
      JA .E6731: ; Required address width 64 can be used in 64bit segment only.
 .A:  IiEmitPrefix ATOGGLE
      RET      
 .32: JECXZ .none:
      CMP CL,2
      JE .none:
      JB .A:
.E6731:Msg '6731' ; Required address width 64 can be used in 64bit segment only.
 .64:  CMP CL,1
       Msg cc=E,'6733' ; Required address width 16 cannot be used in 64bit segment.
       CMP CL,2
       JE .A:
.none: RET
 ENDP IigXLAT::
↑ XLATB
Table Look-up Translation
Description
XLATB
Category
gen,datamov
Operands
AL,BBb
Opcode
0xD7
Tested by
t3203
IigXLATB:: PROC
    IiSuffixed XLAT,B
 ENDP IigXLATB::
↑ XADD
Exchange and Add
Description
XADD
Category
gen,datamov arith,binary
Operands
Eb,Gb | Evqp,Gvqp
Opcode
0x0FC0 ^dw /r | 0x0FC1 ^dW /r
Flags
modified:O..SZAPC, defined:O..SZAPC
CPU
04+
Tested by
t3204
IigXADD:: PROC
    IiRequire 486
    IiAllowLocking Operand1
    IiDataSize
    IiEmitOpcode 0x0F
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat r8.r8, m8.r8, r16.r16, m16.r16, r32.r32, m32.r32, r64.r64, m64.r64
.r8.r8:   
.m8.r8:
    IiEmitOpcode 0xC0
    RET
.r64.r64
.m64.r64:    
.r32.r32:
.m32.r32:
.r16.r16:
.m16.r16:
    IiEmitOpcode 0xC1
    RET
 ENDP IigXADD::
↑ CLC
Clear Carry Flag
Description
CLC
Category
gen,flgctrl
Opcode
0xF8
Flags
modified:.......C, defined:.......C, values:.......C
IigCLC:: PROC
      IiEmitOpcode 0xF8
      IiDispatchFormat none
.none:RET
 ENDP IigCLC::
↑ CLD
Clear Direction Flag
Description
CLD
Category
gen,flgctrl
Opcode
0xFC
Flags
modified:.D......, defined:.D......, values:.D......
IigCLD:: PROC
      IiEmitOpcode 0xFC
      IiDispatchFormat none
.none:RET
 ENDP IigCLD::
↑ CLI
Clear Interrupt Flag
Description
CLI
Category
gen,flgctrl
Opcode
0xFA
Flags
modified:..I....., defined:..I....., values:..I.....
Tested by
t3403
IigCLI:: PROC
      IiEmitOpcode 0xFA
      IiDispatchFormat none
.none:RET
 ENDP IigCLI::
↑ CMC
Complement Carry Flag
Description
CMC
Category
gen,flgctrl
Opcode
0xF5
Flags
tested:.......C, modified:.......C, defined:.......C
IigCMC:: PROC
      IiEmitOpcode 0xF5
      IiDispatchFormat none
.none:RET
 ENDP IigCMC::
↑ STC
Set Carry Flag
Description
STC
Category
gen,flgctrl
Opcode
0xF9
Flags
modified:.......C, defined:.......C, values:.......C
IigSTC:: PROC
      IiEmitOpcode 0xF9
      IiDispatchFormat none
.none:RET
 ENDP IigSTC::
↑ STD
Set Direction Flag
Description
STD
Category
gen,flgctrl
Opcode
0xFD
Flags
modified:.D......, defined:.D......, values:.D......
IigSTD:: PROC
      IiEmitOpcode 0xFD
      IiDispatchFormat none
.none:RET
 ENDP IigSTD::
↑ STI
Set Interrupt Flag
Description
STI
Category
gen,flgctrl
Opcode
0xFB
Flags
modified:..I....., defined:..I....., values:..I.....
IigSTI:: PROC
      IiEmitOpcode 0xFB
      IiDispatchFormat none
.none:RET
 ENDP IigSTI::
↑ HLT
Halt
Description
HLT
Category
system
Opcode
0xF4
Tested by
t3403
IigHLT:: PROC
      IiRequire 086,PRIV
      IiEmitOpcode 0xF4
      IiDispatchFormat none
.none:RET     
 ENDP IigHLT::
↑ CPUID
CPU Identification
Description
CPUID
Category
gen,control
Operands
I...,EAX,ECX,...
Opcode
0x0FA2
CPU
04++
IigCPUID:: PROC
      IiRequire 586
      IiEmitOpcode 0x0F,0xA2
      IiDispatchFormat none
.none:RET
 ENDP IigCPUID::
↑ LAHF
Load Status Flags into AH Register
Description
LAHF
Category
gen,datamov flgctrl
Operands
AH
Opcode
0x9F
Flags
tested:...SZAPC
Documented
D5
Tested by
t3327
IigLAHF:: PROC
      IiAbortIf64
      IiEmitOpcode 0x9F
      IiDispatchFormat none
.none:RET
 ENDP IigLAHF::
↑ SAHF
Store AH into Flags
Description
SAHF
Category
gen,datamov flgctrl
Operands
AH
Opcode
0x9E
Flags
modified:...SZAPC, defined:...SZAPC
Documented
D5
Tested by
t3327
IigSAHF:: PROC
      IiAbortIf64
      IiEmitOpcode 0x9E
      IiDispatchFormat none
.none:RET
 ENDP IigSAHF::
↑ SALC
Set AL If Carry
Alias
IigSETALC
Category
gen,datamov
Operands
AL
Opcode
0xD6
Flags
tested:.......C
CPU
02+
Documented
U7 www.rcollins.org/secrets/opcodes/SALC.html
Tested by
t3327
IigSALC:: PROC
      IiAbortIf64
      IiRequire 086,UNDOC
      IiEmitOpcode 0xD6
      IiDispatchFormat none
.none:RET
 ENDP IigSALC::
↑ SETALC
Set AL If Carry
Alias
IigSALC
Category
gen,datamov
Operands
AL
Opcode
0xD6
Flags
tested:.......C
CPU
02+
Documented
U7 www.rcollins.org/secrets/opcodes/SALC.html
Tested by
t3327
IigSETALC:: PROC
      JMP IigSALC:
 ENDP IigSETALC::
↑ CWD
Sign-extend AX to DX:AX
Description
CWD
Category
gen,conver
Opcode
0x99
Tested by
t3181
IigCWD:: PROC
      IiEncoding DATA=DWORD
      IiEmitOpcode 0x99
      IiDispatchWidth BITS16=.F:
      IiEmitPrefix OTOGGLE
  .F: IiDispatchFormat none
.none:RET
 ENDP IigCWD::
↑ CDQ
Sign-extend EAX to EDX:EAX
Description
CDQ
Category
gen,conver
Opcode
0x99
CPU
03+
Tested by
t3181
IigCDQ:: PROC
      IiRequire 386
      IiEncoding DATA=QWORD
      IiEmitOpcode 0x99
      IiDispatchWidth BITS32=.F:, BITS64=.F:
      IiEmitPrefix OTOGGLE
   .F:IiDispatchFormat none
.none:RET
 ENDP IigCDQ::
↑ CQO
Sign-extend RAX to RDX:RAX
Description
CQO
Category
gen,conver
Opcode
0x99
CPU
P4+
Tested by
t3181
IigCQO:: PROC
      IiAbortIfNot64
      IiEncoding DATA=OWORD
      IiEmitPrefix REX.W
      IiEmitOpcode 0x99
      IiDispatchFormat none
.none:RET
 ENDP IigCQO::
↑ CBW
Sign-extend AL to AX
Description
CBW
Category
gen,conver
Opcode
0x98
Tested by
t3181
IigCBW:: PROC
      IiEncoding DATA=WORD
      IiEmitOpcode 0x98
      IiDispatchWidth BITS16=.F:
      IiEmitPrefix OTOGGLE
  .F: IiDispatchFormat none
.none:RET
 ENDP IigCBW::
↑ CWDE
Sign-extend AX to EAX
Description
CWDE
Category
gen,conver
Opcode
0x98
CPU
P4+
Tested by
t3181
IigCWDE:: PROC
      IiRequire 386
      IiEncoding DATA=DWORD
      IiEmitOpcode 0x98
      IiDispatchWidth BITS32=.F:, BITS64=.F:
      IiEmitPrefix OTOGGLE
   .F:IiDispatchFormat none
.none:RET
 ENDP IigCWDE::
↑ CDQE
Sign-extend EAX to RAX
Description
CDQE
Category
gen,conver
Opcode
0x98
CPU
P4+
Tested by
t3181
IigCDQE:: PROC
      IiAbortIfNot64
      IiEncoding DATA=QWORD
      IiEmitPrefix REX.W
      IiEmitOpcode 0x98
      IiDispatchFormat none
.none:RET
 ENDP IigCDQE::
↑ LEA
Load Effective Address
Description
LEA
Category
gen,datamov
Operands
Gvqp,M
Opcode
0x8D /r
Tested by
t3185
IigLEA:: PROC
    IiDataSize Operand1,SpecifyMem=OFF
    IiEmitOpcode 0x8D
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat r16.mem, r32.mem, r64.mem
.r16.mem:
.r32.mem:
.r64.mem:
    RET
 ENDP IigLEA::
↑ LDS
Load Far Pointer
Description
LDS
Category
gen,datamov segreg
Operands
DS,Gv,Mp
Opcode
0xC5 /r
Tested by
t3186
IigLDS:: PROC
         MOV AL,0xC5
 .op:    IiAbortIf64
         IiEmitOpcode EAX
         IiOpEn RM
         IiModRM /r
         IiDataSize
         IiDispatchFormat r16.m16, r32.m32
.r16.m16:
.r32.m32:RET
 ENDP IigLDS::
↑ LES
Load Far Pointer
Description
LES
Category
gen,datamov segreg
Operands
ES,Gv,Mp
Opcode
0xC4 /r
Tested by
t3186
IigLES:: PROC
         MOV AL,0xC4
         JMP IigLDS.op:
 ENDP IigLES::
↑ LSS
Load Far Pointer
Description
LSS
Category
gen,datamov segreg
Operands
SS,Gvqp,Mptp
Opcode
0x0FB2 ^sRe /r
CPU
03+
Documented
D35
Tested by
t3186
IigLSS:: PROC
         MOV AL,0xB2
 .op:    IiRequire 386
         IiEmitOpcode 0x0F,EAX
         IiOpEn RM
         IiModRM /r
         IiDataSize
         IiDispatchFormat r16.m16, r32.m32, r64.m64
.r64.m64:
.r32.m32:
.r16.m16:RET
 ENDP IigLSS::
↑ LFS
Load Far Pointer
Description
LFS
Category
gen,datamov segreg
Operands
FS,Gvqp,Mptp
Opcode
0x0FB4 ^Sre /r
CPU
03+
Documented
D35
Tested by
t3186
IigLFS:: PROC
         MOV AL,0xB4
         JMP IigLSS.op:
       ENDP IigLFS::
↑ LGS
Load Far Pointer
Description
LGS
Category
gen,datamov segreg
Operands
GS,Gvqp,Mptp
Opcode
0x0FB5 ^SrE /r
CPU
03+
Documented
D35
Tested by
t3186
IigLGS:: PROC
         MOV AL,0xB5
         JMP IigLSS.op:
 ENDP IigLGS::
↑ AAA
ASCII Adjust After Addition
Description
AAA
Category
gen,arith,decimal
Operands
AL,AH
Opcode
0x37
Flags
tested:.....A.., modified:O..SZAPC, defined:.....A.C, undefined:O..SZ.P.
Tested by
t3182
IigAAA:: PROC
      IiAbortIf64
      IiEmitOpcode 0x37
      IiDispatchFormat none
.none:RET
 ENDP IigAAA::
↑ AAS
ASCII Adjust AL After Subtraction
Description
AAS
Category
gen,arith,decimal
Operands
AL,AH
Opcode
0x3F
Flags
tested:.....A.., modified:O..SZAPC, defined:.....A.C, undefined:O..SZ.P.
Tested by
t3182
IigAAS:: PROC
      IiAbortIf64
      IiEmitOpcode 0x3F
      IiDispatchFormat none
.none:RET
 ENDP IigAAS::
↑ AAM
ASCII Adjust AX After Multiply
Description
AAM
Category
gen,arith,decimal
Operands
AL,AH
Opcode
0xD40A
Flags
modified:O..SZAPC, defined:...SZ.P., undefined:O....A.C
Tested by
t3182
IigAAM:: PROC
      IiAbortIf64
      IiEmitOpcode 0xD4
      IiDispatchFormat none,imm
.none:IiAssumeEmpty Operand1, 10
.imm: IiEmitImm Operand1,BYTE
      RET
 ENDP IigAAM::
↑ AAD
ASCII Adjust AX Before Division
Description
AAD
Category
gen,arith,decimal
Operands
AL,AH
Opcode
0xD50A
Flags
modified:O..SZAPC, defined:...SZ.P., undefined:O....A.C
Tested by
t3182
IigAAD:: PROC
      IiAbortIf64
      IiEmitOpcode 0xD5
      IiDispatchFormat none,imm
.none:IiAssumeEmpty Operand1, 10
.imm: IiEmitImm Operand1,BYTE
      RET
 ENDP IigAAD::
↑ DAA
Decimal Adjust AL after Addition
Description
DAA
Category
gen,arith,decimal
Operands
AL
Opcode
0x27
Flags
tested:.....A.C, modified:O..SZAPC, defined:...SZAPC, undefined:O.......
Tested by
t3182
IigDAA:: PROC
      IiAbortIf64
      IiEmitOpcode 0x27
      IiDispatchFormat none
.none:RET
 ENDP IigDAA::
↑ DAS
Decimal Adjust AL after Subtraction
Description
DAS
Category
gen,arith,decimal
Operands
AL
Opcode
0x2F
Flags
tested:.....A.C, modified:O..SZAPC, defined:...SZAPC, undefined:O.......
Tested by
t3182
IigDAS:: PROC
      IiAbortIf64
      IiEmitOpcode 0x2F
      IiDispatchFormat none
.none:RET
 ENDP IigDAS::
↑ BTC
Bit Test and Complement
Description
BTC
Category
gen,bit
Operands
Evqp,Ib | Evqp,Gvqp
Opcode
0x0FBA /7 | 0x0FBB /r
Flags
modified:O..SZAPC, defined:.......C, undefined:O..SZAP.
CPU
03+
Tested by
t3336
IigBTC:: PROC
     MOV AX,0x07BB
.lop:IiAllowLocking Operand1
 .op:IiRequire 386
     IiDataSize
     IiEmitOpcode 0x0F
     IiDispatchFormat r16.r16, m16.r16, r32.r32, m32.r32, r64.r64, m64.r64, \
     r16.imm, r32.imm, r64.imm, m16.imm, m32.imm, m64.imm
.r16.r16:
.m16.r16:
.r32.r32:
.m32.r32:
.r64.r64:
.m64.r64:
     IiEmitOpcode EAX
     IiOpEn MR
     IiModRM /r
     RET
.r16.imm:
.m16.imm:
.r32.imm:
.m32.imm:
.r64.imm:
.m64.imm
     SHL EAX,20
     AND EAX,iiPpgModDigit
     SetSt EAX,iiPpgModRMd
     IiEmitOpcode 0xBA
     IiOpEn M
     IiModRM EAX
     IiEmitImm Operand2, BYTE
     RET
 ENDP IigBTC::
↑ BTCW
Bit Test and Complement WORD
Tested by
t3336
IigBTCW:: PROC
    IiSuffixed BTC,W
 ENDP IigBTCW::
↑ BTCD
Bit Test and Complement DWORD
Tested by
t3336
IigBTCD:: PROC
    IiSuffixed BTC,D    
 ENDP IigBTCD::
↑ BTCQ
Bit Test and Complement QWORD
Tested by
t3336
IigBTCQ:: PROC
    IiSuffixed BTC,Q
 ENDP IigBTCQ::
↑ BT
Bit Test
Description
BT
Category
gen,bit
Operands
Evqp,Gvqp | Evqp,Ib
Opcode
0x0FA3 /r | 0x0FBA /4
Flags
modified:O..SZAPC, defined:.......C, undefined:O..SZAP.
CPU
03+
Tested by
t3333
IigBT:: PROC
     MOV AX,0x04A3
     JMP IigBTC.op:
 ENDP IigBT::
↑ BTW
Bit Test WORD
Tested by
t3333
IigBTW:: PROC
    IiSuffixed BT,W
 ENDP IigBTW::
↑ BTD
Bit Test DWORD
Tested by
t3333
IigBTD:: PROC
    IiSuffixed BT,D    
 ENDP IigBTD::
↑ BTQ
Bit Test QWORD
Tested by
t3333
IigBTQ:: PROC
    IiSuffixed BT,Q    
 ENDP IigBTQ::
↑ BTR
Bit Test and Reset
Description
BTR
Category
gen,bit
Operands
Evqp,Gvqp | Evqp,Ib
Opcode
0x0FB3 /r | 0x0FBA /6
Flags
modified:O..SZAPC, defined:.......C, undefined:O..SZAP.
CPU
03+
Tested by
t3335
IigBTR:: PROC
     MOV AX,0x06B3
     JMP IigBTC.lop:
 ENDP IigBTR::
↑ BTRW
Bit Test and Reset WORD
Tested by
t3335
IigBTRW:: PROC
    IiSuffixed BTR,W
 ENDP IigBTRW::
↑ BTRD
Bit Test and Reset DWORD
Tested by
t3335
IigBTRD:: PROC
    IiSuffixed BTR,D
 ENDP IigBTRD::
↑ BTRQ
Bit Test and Reset QWORD
Tested by
t3335
IigBTRQ:: PROC
    IiSuffixed BTR,Q
 ENDP IigBTRQ::
↑ BTS
Bit Test and Set
Description
BTS
Category
gen,bit
Operands
Evqp,Gvqp | Evqp,Ib
Opcode
0x0FAB /r | 0x0FBA /5
Flags
modified:O..SZAPC, defined:.......C, undefined:O..SZAP.
CPU
03+
Tested by
t3334
IigBTS:: PROC
     MOV AX,0x05AB
     JMP IigBTC.lop:
 ENDP IigBTS::
↑ BTSW
Bit Test and Set WORD
Tested by
t3334
IigBTSW:: PROC
    IiSuffixed BTS,W 
 ENDP IigBTSW::
↑ BTSD
Bit Test and Set DWORD
Tested by
t3334
IigBTSD:: PROC
    IiSuffixed BTS,D    
 ENDP IigBTSD::
↑ BTSQ
Bit Test and Set QWORD
Tested by
t3334
IigBTSQ:: PROC
    IiSuffixed BTS,Q    
 ENDP IigBTSQ::
↑ BSF
Bit Scan Forward
Description
BSF
Category
gen,bit
Operands
Gvqp,Evqp
Opcode
0x0FBC /r
Flags
modified:O..SZAPC, defined:....Z..., undefined:O..S.APC
CPU
03+
Documented
D37
Tested by
t3332
IigBSF:: PROC
     MOV AL,0xBC
.op: IiEmitOpcode 0x0F,EAX
     IiRequire 386
     IiDataSize
     IiOpEn RM
     IiModRM /r
     IiDispatchFormat r32.r32,r32.m32,r16.r16,r16.m16,r64.r64,r64.m64
.r32.r32:
.r32.m32:
.r16.r16:
.r16.m16:
.r64.r64:
.r64.m64:
      RET
 ENDP IigBSF::
↑ BSR
Bit Scan Reverse
Description
BSR
Category
gen,bit
Operands
Gvqp,Evqp
Opcode
0x0FBD /r
Flags
modified:O..SZAPC, defined:....Z..., undefined:O..S.APC
CPU
03+
Documented
D37
Tested by
t3332
IigBSR:: PROC
    MOV AL,0xBD
    JMP IigBSF.op:
 ENDP IigBSR::
↑ POPCNT
Bit Population Count - Return the Count of Number of Bits Set to 1
Description
POPCNT
Category
gen,bit
Operands
Gvqp,Evqp
Intel reference
POPCNT r32, r32 VEX.128.F3.0F.W0 B8 /r
POPCNT r64, r64 VEX.128.F3.0F.W1 B8 /r
Opcode
0xF30FB8 /r
Flags
modified:O..SZAPC, values:O..S.APC
CPU
C2++
Tested by
t3341 t6246
IigPOPCNT:: PROC
    IiAllowModifier PREFIX
    IiDispatchPrefix VEX=.VEX:
    IiRequire 686,SSE4
    IiEmitPrefix REPE
    MOV AL,0xB8
    JMP IigBSF.op:
.VEX:
    IiRequire AVX512, MVEX, SPEC
    IiOpEn RM
    IiEmitOpcode 0xB8
    IiModRM /r
    IiDispatchFormat  r32.r32, r64.r64
.r32.r32:
    IiEmitPrefix VEX.128.F3.0F.W0
    RET
.r64.r64:
    IiEmitPrefix VEX.128.F3.0F.W1
    RET
 ENDP IigPOPCNT::
↑ LZCNT
Count the Number of Leading Zero Bits
Description
LZCNT
Category
gen,bit
Intel reference
LZCNT r16, r/m16 F3 0F BD /r
LZCNT r32, r/m32 F3 0F BD /r
LZCNT r64, r/m64 REX.W F3 0F BD /r
LZCNT r32, r32 VEX.128.F3.0F.W0 BD /r
LZCNT r64, r64 VEX.128.F3.0F.W1 BD /r
Opcode
0xF30FBD
See also
BSR
Tested by
t3341 t6246
IigLZCNT:: PROC
    IiAllowModifier PREFIX
    IiDispatchPrefix VEX=.VEX:
    IiRequire 686,SSE4
    IiEmitPrefix REPE
    MOV AL,0xBD
    JMP IigBSF.op:
.VEX:IiRequire AVX512, MVEX, ABM
    IiOpEn RM
    IiEmitOpcode 0xBD
    IiModRM /r
    IiDispatchFormat r32.r32, r64.r64
.r32.r32:
    IiEmitPrefix VEX.128.F3.0F.W0
    RET
.r64.r64:
    IiEmitPrefix VEX.128.F3.0F.W1
    RET
 ENDP IigLZCNT::
↑ TZCNT
Count the Number of Trailing Zero Bits
Description
TZCNT
Intel reference
TZCNT r16, r/m16 F3 0F BC /r
TZCNT r32, r/m32 F3 0F BC /r
TZCNT r64, r/m64 REX.W F3 0F BC /r
TZCNT r32, r32 VEX.128.F3.0F.W0 BC /r
TZCNT r64, r64 VEX.128.F3.0F.W1 BC /r
Operands
r, r/mem
Opcode
0xF30FBC
Tested by
t6246
IigTZCNT:: PROC
    IiAllowModifier PREFIX
    IiDispatchPrefix VEX=.VEX:
    IiRequire 686,SSE4
    IiEmitPrefix REPE
    MOV AL,0xBC
    JMP IigBSF.op:
.VEX:IiRequire AVX512, MVEX, ABM
    IiEmitOpcode 0xBC
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat r32.r32, r64.r64
.r32.r32:
    IiEmitPrefix VEX.128.F3.0F.W0
    RET
.r64.r64:
    IiEmitPrefix VEX.128.F3.0F.W1
    RET
  ENDP IigTZCNT::
↑ BOUND
Check Array Index Against Bounds
Description
BOUND
Category
gen,break stack
Operands
Gv,Ma,Fv
Opcode
0x62 ^D /r
Flags
modified:..I....., defined:..I....., values:..I.....
CPU
01+
Tested by
t3206
IigBOUND:: PROC
    IiRequire 186
    IiAbortIf64
    IiEmitOpcode 0x62
    IiOpEn RM
    IiModRM /r
    IiDataSize
    IiDispatchFormat r16.m16, r32.m32
.r32.m32:
.r16.m16:
    RET
 ENDP IigBOUND::
↑ BSWAP
Byte Swap
Description
BSWAP
Category
gen,datamov
Operands
Zvqp
Opcode
0x0FC8 ^+r
CPU
04+
Documented
D39
Tested by
t3205
IigBSWAP:: PROC
    IiRequire 486
    IiDataSize Operand1
    IiDispatchFormat r32, r64
.r32:
.r64:
    MOV EAX,[EDI+II.Operand1+EXP.Low]
    AND AL,iiReg_Ord16
    BTR EAX,3
    JNC .R:
    IiEmitPrefix REX.B
 .R:ADD AL,0xC8
    IiEmitOpcode 0x0F,EAX
    RET
 ENDP IigBSWAP::
↑ IN
Input from Port
Description
IN
Category
gen,inout
Operands
AL,Ib | eAX,Ib | AL,DX | eAX,DX
Opcode
0xE4 ^w | 0xE5 ^W | 0xEC ^w | 0xED ^W
Tested by
t3208
IigIN:: PROC
    IiRequire PRIV
    IiAllowModifier IMM
    IiDataSize Operand1
    IiDispatchNotAccum Operand1, .E6763:
    IiDispatchFormat r8.r16, r16.r16, r32.r16, r8.imm, r16.imm, r32.imm
.E6763:IiAbort '6763' ; Only AL/AX/EAX can be used in I/O instruction.
.r8.r16:
.r16.r16:
.r32.r16:
    IiAbortIfNot Operand2,DX
    MOV AL,0xEC
    CMP DH,r8:
    JE .D:
    INC EAX
 .D:IiEmitOpcode EAX ; 0xEC or 0xED
    RET
.r8.imm:
.r16.imm:
.r32.imm:
    MOV AL,0xE4
    CMP DH,r8:
    JE .E:
    INC EAX
 .E:IiEmitOpcode EAX ; 0xE4 or 0xE5
    IiEmitImm Operand2,BYTE
    RET
 ENDP IigIN::
↑ OUT
Output to Port
Description
OUT
Category
gen,inout
Operands
Ib,AL | Ib,eAX | DX,AL | DX,eAX
Opcode
0xE6 ^w | 0xE7 ^W | 0xEE ^w | 0xEF ^W
Tested by
t3208
IigOUT:: PROC
    IiRequire PRIV
    IiAllowModifier IMM
    IiDataSize Operand2
    IiDispatchNotAccum Operand2, .E6763:
    IiDispatchFormat r16.r8, r16.r16, r16.r32, imm.r8, imm.r16, imm.r32
.E6763:IiAbort '6763' ; Only AL/AX/EAX can be used in I/O instruction.
.r16.r8:
.r16.r16:
.r16.r32:
    IiAbortIfNot Operand1,DX
    MOV AL,0xEE
    CMP DL,r8:
    JE .D:
    INC EAX
 .D:IiEmitOpcode EAX ; 0xEE or 0xEF
    RET
.imm.r8:
.imm.r16:
.imm.r32:
    MOV AL,0xE6
    CMP DL,r8:
    JE .E:
    INC EAX
 .E:IiEmitOpcode EAX ; 0xE6 or 0xE7.
    IiEmitImm Operand1,BYTE
    RET
 ENDP IigOUT::
↑ CMPS
Compare String Operands
Description
CMPS
Category
gen,arith string,binary
Operands
Yb,Xb | Ywo,Xwo | Yv,Xv | Yvqp,Xvqp
Opcode
0xA6 ^w | 0xA7 ^W | 0xA7 ^W | 0xA7 ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3214
IigCMPS:: PROC
      IiAllowPrefix RepAny,SegAny
      IiDataSize Operand1+Operand2, SpecifyMem=OFF
      MOV AL,0xA6
      IiDispatchData BYTE=.B:
      INC EAX ; 0xA7
 .B:  IiEmitOpcode EAX
      IiDispatchFormat none, mem.mem
.mem.mem:
      IiStringSource Operand1
      IiStringDestination Operand2
      MOV EAX,[EDI+II.Operand1+EXP.Status]
      MOV ECX,[EDI+II.Operand2+EXP.Status]
      MOV EDX,expAwidth
      AND EAX,EDX
      JZ .none:
      AND ECX,EDX
      JZ .none:
      CMP EAX,ECX
      JE .none:
      Msg '6759' ; Address width of both operands must be the same.
.none:RET

 ENDP IigCMPS::
↑ CMPSB
Compare BYTE String Operands
Description
CMPSB
Category
gen,arith string,binary
Operands
Yb,Xb
Opcode
0xA6 ^w
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3214
IigCMPSB:: PROC
    IiSuffixed CMPS,B
 ENDP IigCMPSB::
↑ CMPSW
Compare WORD String Operands
Description
CMPSW
Category
gen,arith string,binary
Operands
Ywo,Xwo | Ywo,Xwo
Opcode
0xA7 ^W | 0xA7 ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3214
IigCMPSW:: PROC
    IiSuffixed CMPS,W
 ENDP IigCMPSW::
↑ CMPSD
Compare DWORD String Operands overloaded with
Compare Packed Double-FP Values
Description
CMPSD
Category
gen,arith string,binary
Operands
Ydo,Xdo | Ydo,Xdo | Vsd,Wsd,Ib
Opcode
0xA7 ^W | 0xA7 ^W | 0xF20FC2 /r
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
CPU
03+
Tested by
t3214
IigCMPSD:: PROC
    IiRequire 386
    CMP EDX,xmm.xmm.imm
    JE IipCMPSD::
    CMP EDX,xmm.mem.imm
    JE IipCMPSD::
    IiSuffixed CMPS,D
 ENDP IigCMPSD::
↑ CMPSQ
Compare QWORD String Operands
Description
CMPSQ
Category
gen,arith string,binary
Operands
Yqp,Xqp
Opcode
0xA7 ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
CPU
P4+
Tested by
t3214
IigCMPSQ:: PROC
    IiRequire X64
    IiSuffixed CMPS,Q
 ENDP IigCMPSQ::
↑ LODS
Load from String
Description
LODS
Category
gen,datamov string
Operands
AL,Xb | AX,Xwo | eAX,Xv | rAX,Xvqp
Opcode
0xAC ^w | 0xAD ^W | 0xAD ^W | 0xAD ^W
Flags
tested:.D......
Tested by
t3211
IigLODS:: PROC
      IiAllowPrefix RepAny,SegAny
      IiDataSize SpecifyMem=OFF
      MOV AL,0xAC
      IiDispatchData BYTE=.B:
      INC EAX ; 0xAD
  .B: IiEmitOpcode EAX
      IiDispatchFormat none, mem, r8:, r16, r32, r64, r8.mem, r16.mem, r32.mem, r64.mem
.E6755:Msg '6755',EAX ; Unexpected !1R. Only accumulator register AL/AX/EAX/RAX is accepted here.
      RET
.mem: IiStringSource Operand1
      RET
.r8.mem:
.r16.mem:
.r32.mem:
.r64.mem:
      IiStringSource Operand2
.r8:
.r16:
.r32:
.r64: MOV EAX,[EDI+II.Operand1+EXP.Low]
      IiDispatchNotAccum Operand1,.E6755:
.none:RET
     ENDP IigLODS::
↑ LODSB
Load BYTE from String
Description
LODSB
Category
gen,datamov string
Operands
AL,Xb
Opcode
0xAC ^w
Flags
tested:.D......
Tested by
t3211
IigLODSB:: PROC
    IiSuffixed LODS,B
 ENDP IigLODSB::
↑ LODSW
Load WORD from String
Description
LODSW
Category
gen,datamov string
Operands
AX,Xwo | AX,Xwo
Opcode
0xAD ^W | 0xAD ^W
Flags
tested:.D......
Tested by
t3211
IigLODSW:: PROC
    IiSuffixed LODS,W
 ENDP IigLODSW::
↑ LODSD
Load DWORD from String
Description
LODSD
Category
gen,datamov string
Operands
EAX,Xdo | EAX,Xdo
Opcode
0xAD ^W | 0xAD ^W
Flags
tested:.D......
CPU
03+
Tested by
t3211
IigLODSD:: PROC
    IiRequire 386
    IiSuffixed LODS,D
 ENDP IigLODSD::
↑ LODSQ
Load QWORD from String
Description
LODSQ
Category
gen,datamov string
Operands
RAX,Xqp
Opcode
0xAD ^W
Flags
tested:.D......
CPU
P4+
Tested by
t3211
IigLODSQ:: PROC
    IiRequire X64
    IiSuffixed LODS,Q
 ENDP IigLODSQ::
↑ MOVS
Move Data from String to String.
Description
MOVS
Category
gen,datamov string
Operands
Yb,Xb | Ywo,Xwo | Yv,Xv | Yvqp,Xvqp
Opcode
0xA4 ^w | 0xA5 ^W | 0xA5 ^W | 0xA5 ^W
Flags
tested:.D......
Tested by
t3213
IigMOVS:: PROC
      CMP DL,xmm
      JE .SSE:
      CMP DH,xmm
      JE .SSE:
.STR: IiAllowPrefix RepAny,SegAny
      IiDataSize Operand1+Operand2,SpecifyMem=OFF
      MOV AL,0xA4
      IiDispatchData BYTE=.B:
      INC EAX ; 0xA5
  .B: IiEmitOpcode EAX
      IiDispatchFormat none, mem.mem
.mem.mem:
      IiStringDestination Operand1
      IiStringSource      Operand2
      MOV EAX,[EDI+II.Operand1+EXP.Status]
      MOV ECX,[EDI+II.Operand2+EXP.Status]
      MOV EDX,expAwidth
      AND EAX,EDX
      JZ .none:
      AND ECX,EDX
      JZ .none:
      CMP EAX,ECX
      JE .none:
      Msg '6759' ; Address width of both operands must be the same.
.none:RET
.SSE: JNSt  [EDI+II.MfgSuffix],iiMfgDATA_DWORD, .STR:
      RstSt [EDI+II.MfgSuffix],iiMfgDATA_DWORD
      IiAllowModifier CODE
      IiEmitPrefix REPNE
      IiEmitOpcode 0x0F
      IiModRM /r
      IiDispatchFormat xmm.mem, mem.xmm, xmm.xmm
.mem.xmm:
      IiEmitOpcode 0x11
      IiEncoding CODE=LONG,DATA=QWORD
      IiOpEn MR
      RET
.xmm.xmm:
      IiDispatchCode LONG=.mem.xmm:
.xmm.mem:
      IiEmitOpcode 0x10
      IiEncoding CODE=SHORT,DATA=QWORD
      IiOpEn RM
      RET
 ENDP IigMOVS::
↑ MOVSB
Move BYTE Data from String to String
Description
MOVSB
Category
gen,datamov string
Operands
Yb,Xb
Opcode
0xA4 ^w
Flags
tested:.D......
Tested by
t3213
IigMOVSB:: PROC
    IiSuffixed MOVS,B
 ENDP IigMOVSB::
↑ MOVSW
Move WORD Data from String to String
Description
MOVSW
Category
gen,datamov string
Operands
Ywo,Xwo | Ywo,Xwo
Opcode
0xA5 ^W | 0xA5 ^W
Flags
tested:.D......
Tested by
t3213
IigMOVSW:: PROC
    IiSuffixed MOVS,W
 ENDP IigMOVSW::
↑ MOVSD
Move DWORD Data from String to String. Move or Merge Scalar Double-Precision Floating-Point value.
Description
MOVSB, MOVSD
Category
gen,datamov string
Operands
Ydo,Xdo | Ydo,Xdo | Vsd,Wsd | Wsd,Vsd
Opcode
0xA5 ^W | 0xA5 ^W | 0xF20F10 /r | 0xF20F11 /r
Flags
tested:.D......
CPU
03+
Tested by
t3213
IigMOVSD:: PROC
    IiRequire 386
    IiSuffixed MOVS,D
 ENDP IigMOVSD::
↑ MOVSQ
Move QWORD Data from String to String
Description
MOVSQ
Category
gen,datamov string
Operands
Yqp,Xqp
Opcode
0xA5 ^W
Flags
tested:.D......
CPU
P4+
Tested by
t3213
IigMOVSQ:: PROC
    IiRequire X64
    IiSuffixed MOVS,Q
 ENDP IigMOVSQ::
↑ SCAS
Scan String
Description
SCAS
Category
gen,arith string,binary
Operands
Yb,AL | Ywo,AX | Yv,eAX | Yvqp,rAX
Opcode
0xAE ^w | 0xAF ^W | 0xAF ^W | 0xAF ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3212
IigSCAS:: PROC
    IiAllowPrefix RepAny,SEGES
    IiDataSize SpecifyMem=OFF
    MOV AL,0xAE
    IiDispatchData BYTE=.B:
    INC EAX
 .B:IiEmitOpcode EAX
    IiDispatchFormat none, mem, mem.r8, mem.r16, mem.r32, mem.r64
.E6755:Msg '6755',EAX; Unexpected !1R. Only accumulator register AL/AX/EAX/RAX is accepted here.
    RET
.mem.r8:
.mem.r16:
.mem.r32:
.mem.r64:
      MOV EAX,[EDI+II.Operand2+EXP.Low]
      IiDispatchNotAccum Operand2,.E6755:
.mem: IiStringDestination Operand1
.none:RET
 ENDP IigSCAS::
↑ SCASB
Scan BYTE in String
Description
SCASB
Category
gen,arith string,binary
Operands
Yb,AL
Opcode
0xAE ^w
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3212
IigSCASB:: PROC
    IiSuffixed SCAS,B
 ENDP IigSCASB::
↑ SCASW
Scan WORD in String
Description
SCASW
Category
gen,arith string,binary
Operands
Ywo,AX | Ywo,AX
Opcode
0xAF ^W | 0xAF ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
Tested by
t3212
IigSCASW:: PROC
    IiSuffixed SCAS,W
 ENDP IigSCASW::
↑ SCASD
Scan DWORD in String
Description
SCASD
Category
gen,arith string,binary
Operands
Ydo,EAX | Ydo,EAX
Opcode
0xAF ^W | 0xAF ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
CPU
03+
Tested by
t3212
IigSCASD:: PROC
    IiRequire 386
    IiSuffixed SCAS,D
 ENDP IigSCASD::
↑ SCASQ
Scan QWORD in String
Category
gen,arith string,binary
Operands
Yqp,RAX
Opcode
0xAF ^W
Flags
tested:.D......, modified:O..SZAPC, defined:O..SZAPC
CPU
P4+
Tested by
t3212
IigSCASQ:: PROC
    IiRequire X64
    IiSuffixed SCAS,Q
 ENDP IigSCASQ::
↑ INS
Input from Port to String
Description
INS
Category
gen,inout string
Operands
Yb,DX | Ywo,DX | Yv,DX
Opcode
0x6C ^w | 0x6D ^W | 0x6D ^W
Flags
tested:.D......
CPU
01+
Tested by
t3215
IigINS:: PROC
      IiRequire 186,PRIV
      IiAllowPrefix RepAny,SEGES
      IiDataSize Operand1,SpecifyMem=OFF
      IiRemoveREXW
      MOV AL,0x6C
      IiDispatchData BYTE=.B:
      INC EAX ; 0x6D
  .B: IiEmitOpcode EAX
      IiDispatchFormat none, mem, mem.r16
.mem.r16:IiAbortIfNot Operand2,DX
.mem: IiStringDestination Operand1
.none:RET
 ENDP IigINS::
↑ INSB
Input BYTE from Port to String
Description
INSB
Category
gen,inout string
Operands
Yb,DX
Opcode
0x6C ^w
Flags
tested:.D......
CPU
01+
Tested by
t3215
IigINSB:: PROC
    IiSuffixed INS,B
 ENDP IigINSB::
↑ INSW
Input WORD from Port to String
Description
INSW
Category
gen,inout string
Operands
Ywo,DX
Opcode
0x6D ^W
Flags
tested:.D......
CPU
01+
Tested by
t3215
IigINSW:: PROC
    IiSuffixed INS,W
 ENDP IigINSW::
↑ INSD
Input DWORD from Port to String
Description
INSD
Category
gen,inout string
Operands
Ydo,DX
Opcode
0x6D ^W
Flags
tested:.D......
CPU
03+
Tested by
t3215
IigINSD:: PROC
    IiRequire 386
    IiSuffixed INS,D
 ENDP IigINSD::
↑ OUTS
Output String to Port
Description
OUTS
Category
gen,inout string
Operands
DX,Xb | DX,Xwo | DX,Xv
Opcode
0x6E ^w | 0x6F ^W | 0x6F ^W
Flags
tested:.D......
CPU
01+
Tested by
t3216
IigOUTS:: PROC
    IiRequire 186,PRIV
    IiAllowPrefix RepAny,SegAny
    IiDataSize Operand2,SpecifyMem=OFF
    IiRemoveREXW
    MOV AL,0x6E
    IiDispatchData BYTE=.B:
    INC EAX ; 0x6F
 .B:IiEmitOpcode EAX
    IiDispatchFormat none, r16, r16.mem
.r16.mem:IiStringSource Operand2
.r16:IiAbortIfNot Operand1,DX
.none:RET
 ENDP IigOUTS::
↑ OUTSB
Output BYTE String to Port
Description
OUTSB
Category
gen,inout string
Operands
DX,Xb
Opcode
0x6E ^w
Flags
tested:.D......
CPU
01+
Tested by
t3216
IigOUTSB:: PROC
    IiSuffixed OUTS,B
 ENDP IigOUTSB::
↑ OUTSW
Output WORD String to Port
Description
OUTSW
Category
gen,inout string
Operands
DX,Xwo
Opcode
0x6F ^W
Flags
tested:.D......
CPU
01+
Tested by
t3216
IigOUTSW:: PROC
    IiSuffixed OUTS,W
 ENDP IigOUTSW::
↑ OUTSD
Output DWORD String to Port
Description
OUTSD
Category
gen,inout string
Operands
DX,Xdo
Opcode
0x6F ^W
Flags
tested:.D......
CPU
03+
Tested by
t3216
IigOUTSD:: PROC
    IiRequire 386
    IiSuffixed OUTS,D
 ENDP IigOUTSD::
↑ STOS
Store String
Description
STOS
Category
gen,datamov string
Operands
Yb,AL | Ywo,AX | Yv,eAX | Yvqp,rAX
Opcode
0xAA ^w | 0xAB ^W | 0xAB ^W | 0xAB ^W
Flags
tested:.D......
Tested by
t3210
IigSTOS:: PROC
    IiAllowPrefix RepAny,SEGES
    IiDataSize SpecifyMem=OFF
    MOV AL,0xAA
    IiDispatchData BYTE=.B:
    INC EAX
 .B:IiEmitOpcode EAX
    IiDispatchFormat none, mem, mem.r8, mem.r16, mem.r32, mem.r64
.E6755:Msg '6755',EAX; Unexpected !1R. Only accumulator register AL/AX/EAX/RAX is accepted here.
    RET
.mem.r8:
.mem.r16:
.mem.r32:
.mem.r64
     MOV EAX,[EDI+II.Operand2+EXP.Low]
     IiDispatchNotAccum Operand2, .E6755:
.mem:IiStringDestination Operand1
.none:RET
     ENDP IigSTOS::
↑ STOSB
Store BYTE to String
Description
STOSB
Category
gen,datamov string
Operands
Yb,AL
Opcode
0xAA ^w
Flags
tested:.D......
Tested by
t3210
IigSTOSB:: PROC
    IiSuffixed STOS,B
 ENDP IigSTOSB::
↑ STOSW
Store WORD to String
Description
STOSW
Category
gen,datamov string
Operands
Ywo,AX | Ywo,AX
Opcode
0xAB ^W | 0xAB ^W
Flags
tested:.D......
Tested by
t3210
IigSTOSW:: PROC
    IiSuffixed STOS,W
 ENDP IigSTOSW::
↑ STOSD
Store DWORD to String
Description
STOSD
Category
gen,datamov string
Operands
Ydo,EAX | Ydo,EAX
Opcode
0xAB ^W | 0xAB ^W
Flags
tested:.D......
CPU
03+
Tested by
t3210
IigSTOSD:: PROC
    IiSuffixed STOS,D
 ENDP IigSTOSD::
↑ STOSQ
Store QWORD to String
Description
STOSQ
Category
gen,datamov string
Operands
Yqp,RAX
Opcode
0xAB ^W
Flags
tested:.D......
CPU
P4+
Tested by
t3210
IigSTOSQ:: PROC
    IiSuffixed STOS,Q
 ENDP IigSTOSQ::
↑ ICEBP
Emulator INT 1
Operands
-
Opcode
0xF1
CPU
386
Documented
asm.inightmare.org/opcodelst/
Tested by
t3325
IigICEBP:: PROC
    IiAbortIf64
    IiRequire 386,UNDOC
    IiEmitOpcode 0xF1
    IiDispatchFormat none
.none:RET
 ENDP IigICEBP::
↑ PSRAQ
Bit Shift Arithmetic Right
Category
Undocumented. Format xmm,xmm is not available, as opcode 0x660FE3/r is already occupied by PAVGW.
Operands
xmm,imm8
Opcode
0x660F73 /4 ib
Documented
ExtraInstructions.txt
Tested by
t3600
IigPSRAQ:: PROC
    IiRequire 686,SSE,UNDOC
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0x73
    IiOpEn M
    IiModRM /4
    IiEncoding IMM=BYTE,DATA=OWORD
    IiEmitImm Operand2, BYTE
    IiDispatchFormat xmm.imm
.xmm.imm:RET
 ENDP IigPSRAQ::
↑ CMPXCHG8B
Compare and Exchange 8 Bytes
Description
CMPXCHG8B
Category
gen
Operands
mem64
Opcode
0x0FC7 /1
Tested by
t3222
IigCMPXCHG8B:: PROC
    IiRequire 586
    IiAllowPrefix LOCK
    IiEmitOpcode 0x0F,0xC7
    IiOpEn M
    IiModRM /1
    IiDispatchFormat mem
.mem:RET
 ENDP IigCMPXCHG8B::
↑ CMPXCHG16B
Compare and Exchange 16 Bytes
Description
CMPXCHG16B
Category
gen
Operands
mem128
Opcode
REX.W 0x0FC7 /1
Tested by
t3222
IigCMPXCHG16B:: PROC
    IiRequire X64
    IiAbortIfNot64
    IiAllowPrefix LOCK
    IiEmitPrefix REX.W
    IiEmitOpcode 0x0F,0xC7
    IiOpEn M
    IiModRM /1
    IiDispatchFormat mem
.mem:RET
 ENDP IigCMPXCHG16B::
↑ CMPXCHG486
Compare and Exchange
Category
deprecated
Opcode
0xA6 || 0xA7
CPU
486A only. Use CMPXCHG instead on newer CPUs.
Tested by
t3221
IigCMPXCHG486:: PROC
    IiRequire 486, UNDOC
    IiAllowLocking Operand1
    IiDataSize
    MOV AL,0xA6
    IiDispatchData BYTE=.B:
    INC EAX
 .B:IiEmitOpcode 0x0F,EAX
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat r8.r8,m8.r8,r16.r16,m16.r16,r32.r32,m32.r32
.m32.r32:
.m16.r16:
.r32.r32:
.r16.r16:
.m8.r8:
.r8.r8:
    RET
 ENDP IigCMPXCHG486::
↑ CMPXCHG
Compare and Exchange
Description
CMPXCHG
Category
gen,datamov arith,binary
Operands
Eb,AL,Gb | Evqp,rAX,Gvqp
Opcode
0x0FB0 ^dw /r | 0x0FB1 ^dW /r
Flags
modified:O..SZAPC, defined:O..SZAPC
CPU
04+
Documented
D34
Tested by
t3221
IigCMPXCHG:: PROC
    IiRequire 486
    IiDataSize
    IiAllowLocking Operand1
    MOV AL,0xB0
    IiDispatchData BYTE=.B:
    INC EAX ; 0xB1
 .B:IiEmitOpcode 0x0F,EAX
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat r8.r8,m8.r8,r16.r16,m16.r16,r32.r32,m32.r32,r64.r64,m64.r64
.m64.r64:
.m32.r32:
.m16.r16:
.r64.r64:
.r32.r32:
.r16.r16:
.m8.r8:
.r8.r8:
    RET
 ENDP IigCMPXCHG::
↑ ENTER
Make Stack Frame for Procedure Parameters
Description
ENTER
Category
gen,stack
Operands
eBP,Iw,Ib | rBP,Iw,Ib
Opcode
0xC8 | 0xC8
CPU
01+
Tested by
t3442
IigENTER:: PROC
    IiRequire 186
    IiAllowModifier IMM,DATA
    IiEmitOpcode 0xC8
    IiEmitImm  Operand1, WORD
    IiEmitImm2 Operand2, Max=31
    IiDataSize UseSegment=ON
    IiRemoveREXW
    IiDispatchFormat imm.imm
.E6732:Msg '6732' ; Required operand width 64 can be used in 64bit segment only.    
    RET
.E6736:Msg '6736' ; Required operand width 32 of this instruction cannot be used in 64bit mode.
    IiEncoding DATA=QWORD
    RET    
.imm.imm:
    IiDispatchWidth BITS64=.64
    RET
.64:IiDispatchData DWORD=.E6736:
    RET 
 ENDP IigENTER::
↑ ENTERW
Make Stack Frame for Procedure Parameters, WORD pointers
Tested by
t3442
IigENTERW:: PROC
    IiSuffixed ENTER,W
 ENDP IigENTERW::
↑ ENTERD
Make Stack Frame for Procedure Parameter, DWORD pointers
Tested by
t3442
IigENTERD:: PROC
    IiSuffixed ENTER,D
 ENDP IigENTERD::
↑ ENTERQ
Make Stack Frame for Procedure Parameter, QWORD pointers
Tested by
t3442
IigENTERQ:: PROC
    IiSuffixed ENTER,Q
 ENDP IigENTERQ::
↑ LEAVE
High Level Procedure Exit
Description
LEAVE
Category
gen,stack
Operands
eBP | rBP
Opcode
0xC9 | 0xC9
CPU
01+
Tested by
t3442
IigLEAVE:: PROC
    IiRequire 186
    IiAllowModifier DATA
    IiEmitOpcode 0xC9
    IiDataSize UseSegment=ON
    IiRemoveREXW
    IiDispatchFormat none
.E6736:Msg '6736' ; Required operand width 32 of this instruction cannot be used in 64bit mode.
    IiEncoding DATA=QWORD
    RET
.none:
    IiDispatchWidth BITS64=.64
    RET
.64:IiDispatchData DWORD=.E6736:
    RET 
 ENDP IigLEAVE::
↑ LEAVEW
High Level Procedure Exit, WORD pointers
Tested by
t3442
IigLEAVEW:: PROC
    IiSuffixed LEAVE,W
 ENDP IigLEAVEW::
↑ LEAVED
High Level Procedure Exit, DWORD pointers
Tested by
t3442
IigLEAVED:: PROC
    IiSuffixed LEAVE,D
 ENDP IigLEAVED::
↑ LEAVEQ
High Level Procedure Exit, QWORD pointers
Tested by
t3442
IigLEAVEQ:: PROC
    IiSuffixed LEAVE,Q
 ENDP IigLEAVEQ::
  ENDPROGRAM iig

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