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This page is hosting links to external documentation and resources used by EuroAssembler project, including errata of mistakes and typos discovered during the €ASM developement.
I cannot guarantee that the provided links will be working forever and that they wil keep the same information as they did when I was reading them. If the link is not available, searching the Internet for a few words from the resource title usually yields the functional alternative locations.
1. In Table 1.10 BPB Fields for FAT32 Volumes instead of
0x34 WORD 0x0600 Backup Boot Sector (FAT32 only)should be
0x32 WORD 0x0600 Backup Boot Sector (FAT32 only)2. In Table 1.10 BPB Fields for FAT32 Volumes instead of
0x36 12 bytes Reserved (FAT32 only)should be
0x34 12 bytes Reserved (FAT32 only)
1. On page 13 (9/ Note sections) instead of
note entries, each of which is an array of 8-byte wordsshould be
note entries, each of which is an array of 4-byte words
1. On page 5-52 (VPBROADCAST) instead of
EVEX.512.66.0F38.W1 5B /rshould be
VBROADCASTI32X8 zmm1 {k1}{z}, m256
EVEX.512.66.0F38.W0 5B /r
VBROADCASTI32X8 zmm1 {k1}{z}, m2562. On page 5-100 (instruction CVTDQ2PD) columns Instruction and Description instead of
VCVTDQ2PD xmm1 {k1}{z},xmm2/m128/m32bcst Convert 2 packed signed doubleword integers from xmm2/m128/m32bcst to eightshould be
VCVTDQ2PD xmm1 {k1}{z},xmm2/m64/m32bcst Convert 2 packed signed doubleword integers from xmm2/m128/m32bcst to two3. On page 5-120 (VCVTPH2PS) column Opcode instead of
1313 /rshould be
13 /r4. On page 5-123 (VCVTPS2PH) column Opcode instead of
1D1D /r ibshould be
1D /r ib5. On page 5-164 instead of
VCVTTPD2UDQ EVEX.256.0F.W1 78 02 /rshould be
VCVTTPD2UDQ EVEX.256.0F.W1 78 /r6. On page 5-175 column Description of VCVTTPS2UQQ xmm1,xmm2 instead of
from zmm2/m64/m32bcstshould be
from xmm2/m64/m32bcst7. On page 5-194 VCVTUSI2SS column Description instead of
Convert one signed doubleword integershould be
Convert one unsigned doubleword integer8. On page 5-295 VFNMADD132PD column Opcode instead of
EVEX.NDS.128.66.0F38.W1 9C /rshould be
VFNMADD132PD xmm0 {k1}{z}, xmm1, xmm2/m128/m64bcst
EVEX.NDS.128.66.0F38.W1 9C /r
VFNMADD132PD xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst9. On page 5-320 VFNMSUB231PS column Opcode instead of
VEX.NDS.256.66.0F38.0 BE /rshould be
VFNMSUB231PS ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F38.W0 BE /r
VFNMSUB231PS ymm1, ymm2, ymm3/m25610. On page 5-339 VFPCLASSSS column Opcode instead of
EVEX.LIG.66.0F3A.W0 67 /rshould be
VFPCLASSSS k2 {k1}, xmm2/m32, imm8
EVEX.LIG.66.0F3A.W0 67 /r ib
VFPCLASSSS k2 {k1}, xmm2/m32, imm811. On pages 5-332, 5-335, 5-337, 5-339 VFPCLASS** in frame Instruction Operand Encoding in column Operand3 instead of
Operand 3 NAshould be
Operand 3 Imm812. On page 5-371 and 5-373 VGETMANTSD and VGETMANTSS in frame Instruction Operand Encoding in column Operand4 instead of
Operand 4 NAshould be
Operand 4 Imm813. On page 5-414 in column Op/En of operations
MOVD xmm1, r32/m32MOVQ xmm1, r64/m64VMOVD xmm1, r32/m32VMOVQ xmm1, r64/m64
instead ofMRshould be
RM14. On page 5-429 instead of
VMOVDQU32 xmm1 {k1}{z}, xmm2/mm128should be
VMOVDQU32 xmm1 {k1}{z}, xmm2/m12815. On page 5-471 VMOVUPS instead of
VEX.128.0F 11.WIG /rshould be
VEX.256.0F 10.WIG /r
VEX.256.0F 11.WIG /r
VEX.128.0F.WIG 11 /r
VEX.256.0F.WIG 10 /r
VEX.256.0F.WIG 11 /r16. On page 5-542 instead of
VEX.NDS.128.66.0F E0should be
VPAVGB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F E3
VPAVGW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F E0
VPAVGB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F E3
VPAVGW ymm1, ymm2, ymm3/m256
VEX.NDS.128.66.0F E0 /r
VPAVGB xmm1, xmm2, xmm3/m128
VEX.NDS.128.66.0F E3 /r
VPAVGW xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F E0 /r
VPAVGB ymm1, ymm2, ymm3/m256
VEX.NDS.256.66.0F E3 /r
VPAVGW ymm1, ymm2, ymm3/m25617. On page 5-689 in column Op/En of instructions VPMOVQD, VPMOVSQD, VPMOVUSQD instead of
Op/En Ashould be
Op/En HVM18. On page 5-802 in column Op/En of instructions
VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst, imm8
VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst, imm8
instead ofFVshould be
FVI19. On page 5-873 in column Instruction instead of
VSQRTPD xmm1 {k1}{z}, xmm2/m128/m32bcstshould be
VSQRTPD ymm1 {k1}{z}, ymm2/m256/m32bcst
VSQRTPD xmm1 {k1}{z}, xmm2/m128/m64bcst
VSQRTPD ymm1 {k1}{z}, ymm2/m256/m64bcst20. On page 5-921 in column Instruction instead of
EVEX.NDS.LIG.66.0F3A.W1 57 /rshould be
VREDUCESD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm8
EVEX.NDS.LIG.66.0F3A.W1 57 /r ib
VREDUCESD xmm1 {k1}{z}, xmm2, xmm3/m64{sae}, imm821. On page 5-921 (instruction VREDUCESD) in frame Instruction Operand Encoding instead of
Operand4 NAshould be
Operand4 Imm822. On page IV of INDEX there is no such instruction on pages 5-562, 5-571. Specification of PCLMULQDQ also mentioned on page 2-27 is missing.
PCLMULQDQ - Carry-Less Multiplication Quadword 5-562, 5-571
1. On page 3-530 Vol.2A (instruction MOV—Move) instead of
REX.W + 8C /r MOV r/m64,Sreg** MR Valid Validshould be
REX.W + 8C /r MOV r/m64,Sreg** MR Valid N.E2. On page 3-530 Vol.2A (instruction MOV—Move) instead of
REX.W + C7 /0 io MOV r/m64, imm32should be
REX.W + C7 /0 id MOV r/m64, imm323. On page 4-184 Vol.2B and on page 4-272 Vol.2B (instruction POP) paragraph Description incorrecly suggests that operand-size of POP and PUSH can be overriden by prefix REX.W:
Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may be overridden by instruction prefixes (66H or REX.W).should be
Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may be overridden by instruction prefix (66H).
1. On page 30-3 Vol.3C (instruction INVEPT) instead of
66 0F 38 80 INVEPT r64, m128should be
66 0F 38 80 /r INVEPT r64, m1282. On page 30-3 Vol.3C (instruction INVEPT) instead of
66 0F 38 80 INVEPT r32, m128should be
66 0F 38 80 /r INVEPT r32, m1283. On page 30-6 Vol.3C (instruction INVVPID) instead of
66 0F 38 81 INVVPID r64, m128should be
66 0F 38 81 /r INVVPID r64, m1284. On page 30-6 Vol.3C (instruction INVVPID) instead of
66 0F 38 81 INVVPID r32, m128should be
66 0F 38 81 /r INVVPID r32, m1285. On page 30-13 Vol.3C (instruction VMFUNC) instead of
NP 0F 01 D4 VMFUNCshould be
0F 01 D4 VMFUNC6. On page 30-16 Vol.3C (instruction VMPTRLD) instead of
NP 0F C7 /6 VMPTRLD m64should be
0F C7 /6 VMPTRLD m647. On page 30-18 Vol.3C (instruction VMPTRST) instead of
NP 0F C7 /7 VMPTRST m64should be
0F C7 /7 VMPTRST m648. On page 30-20 Vol.3C (instruction VMREAD) instead of
NP 0F 78 VMREAD r/m64,r64should be
0F 78 /r VMREAD r/m64,r649. On page 30-20 Vol.3C (instruction VMREAD) instead of
NP 0F 78 VMREAD r/m32,r32should be
0F 78 /r VMREAD r/m32,r3210. On page 30-23 Vol.3C (instruction VMWRITE) instead of
NP 0F 79 VMWRITE r/m64,r64should be
0F 79 /r VMWRITE r/m64,r6411. On page 30-23 Vol.3C (instruction VMWRITE) instead of
NP 0F 79 VMWRITE r/m32,r32should be
0F 79 /r VMWRITE r/m32,r3212. The shortcut NP used many times in Opcode column is not explained on page 3-2 Vol.2A 3.1.1.1 Summary