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iis.htm
Enumerations
IisList
Instruction handlers
ALTINST ARPL BNDCL BNDCN BNDCU BNDLDX BNDMK BNDMOV BNDSTX CL1INVMB CLAC CLFLUSH CLFLUSHOPT CLRSSBSY CLTS CLZERO ENCLS ENCLU ENCLV ENDBR32 ENDBR64 GETSEC HCF HINT_NOP HINT_NOPD HINT_NOPQ HINT_NOPW HRESET IBTS INCSSPD INCSSPQ INVD INVLPG JMPE LAR LFENCE LGDT LIDT LLDT LMSW LOADALL LOADALL286 LSL LTR MFENCE MONITOR MONITORX MWAIT MWAITX NOP NOP1 NOP2 NOP3 NOP4 NOP5 NOP6 NOP7 NOP8 NOP9 PAUSE PREFETCH PREFETCHNTA PREFETCHT0 PREFETCHT1 PREFETCHT2 PREFETCHW PREFETCHWT1 RDMSR RDPKRU RDPMC RDRAND RDSEED RDTSC RDTSCP RSM RSTORSSP SAVEPREVSSP SENDUIPI SERIALIZE SETSSBSY SFENCE SGDT SIDT SLDT SMSW STAC STR SWAPGS SYSCALL SYSENTER SYSEXIT SYSRET UD0 UD1 UD2 UD2A UD2B UMONITOR UMWAIT VERR VERW WBINVD WRMSR WRPKRU XBTS

↑ IisHandlers: assemble system machine instructions.
See also: IiHandlers, [RoseCompiler]

iis PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.
INCLUDEHEAD  \  ; Include headers of another modules used in this module.
ea.htm,      \
eaopt.htm,   \
exp.htm,     \
ii.htm,      \
msg.htm,     \
pgm.htm,     \
pgmopt.htm,  \
sss.htm,     \
stm.htm,     \
sym.htm,     \
syswin.htm,  \
;;

iis HEAD ; Start of module interface.

↑ %IisList: enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IisList requires the corresponding handler in this file.
See also: DictLookupIi

%IisList %SET \
ALTINST, \
ARPL, \
BNDCL, \
BNDCN, \
BNDCU, \
BNDLDX, \
BNDMK, \
BNDMOV, \
BNDSTX, \
CL1INVMB, \
CLAC, \
CLFLUSH, \
CLFLUSHOPT, \
CLRSSBSY, \
CLTS, \
CLZERO, \
ENCLS, \
ENCLU, \
ENCLV, \
ENDBR32, \
ENDBR64, \
GETSEC, \
HCF, \
HINT_NOP, \
HINT_NOPD, \
HINT_NOPQ, \
HINT_NOPW, \
HRESET, \
IBTS, \
INCSSPD, \
INCSSPQ, \
INVD, \
INVLPG, \
JMPE, \
LAR, \
LFENCE, \
LGDT, \
LIDT, \
LLDT, \
LMSW, \
LOADALL, \
LOADALL286, \
LSL, \
LTR, \
MFENCE, \
MONITOR, \
MONITORX, \
MWAIT, \
MWAITX, \
NOP, \
NOP1, \
NOP2, \
NOP3, \
NOP4, \
NOP5, \
NOP6, \
NOP7, \
NOP8, \
NOP9, \
PAUSE, \
PREFETCH, \
PREFETCHNTA, \
PREFETCHT0, \
PREFETCHT1, \
PREFETCHT2, \
PREFETCHW, \
PREFETCHWT1, \
RDMSR, \
RDPKRU, \
RDPMC, \
RDRAND, \
RDSEED, \
RDTSC, \
RDTSCP, \
RSM, \
RSTORSSP, \
SAVEPREVSSP, \
SENDUIPI, \
SERIALIZE, \
SETSSBSY, \
SFENCE, \
SGDT, \
SIDT, \
SLDT, \
SMSW, \
STAC, \
STR, \
SWAPGS, \
SYSCALL, \
SYSENTER, \
SYSEXIT, \
SYSRET, \
UD0, \
UD1, \
UD2, \
UD2A, \
UD2B, \
UMONITOR, \
UMWAIT, \
VERR, \
VERW, \
WBINVD, \
WRMSR, \
WRPKRU, \
XBTS, \

;

  ENDHEAD iis ; End of module interface.

↑ MONITOR: Set Up Monitor Address
Description: MONITOR
Opcode: 0x0F01C8
CPU: P4++
Tested by: t3415 t4140

IisMONITOR:: PROC
    IiRequire 686
    IiEmitOpcode 0x0F,0x01,0xC8
    IiDispatchFormat none
.none:RET
 ENDP IisMONITOR::

↑ MWAIT: Monitor Wait
Description: MWAIT
Category: sync
Opcode: 0x0F01C9
CPU: P4++
Tested by: t3415 t4140

IisMWAIT:: PROC
    IiRequire 686
    IiEmitOpcode 0x0F,0x01,0xC9
    IiDispatchFormat none
.none:RET
 ENDP IisMWAIT::

↑ MONITORX: Setup Monitor Address
Documented: AMD
Tested by: t3415 t4140

IisMONITORX:: PROC
    IiRequire 686,AMD
    IiEmitOpcode 0x0F,0x01,0xFA
    IiDispatchFormat none
.none:RET
 ENDP IisMONITORX::

↑ MWAITX: Monitor Wait with Timeout
Documented: AMD
Tested by: t3415 t4140

IisMWAITX:: PROC
    IiRequire 686,AMD
    IiEmitOpcode 0x0F,0x01,0xFB
    IiDispatchFormat none
.none:RET
 ENDP IisMWAITX::

↑ LFENCE: Load Fence
Description: LFENCE
Category: order
Opcode: 0x0FAEE8
CPU: P4+
Tested by: t3415 t4140

IisLFENCE:: PROC
    IiRequire 686,SSE2
    IiEmitOpcode 0x0F,0xAE,0xE8
    IiDispatchFormat none
.none:RET
 ENDP IisLFENCE::

↑ MFENCE: Memory Fence
Description: MFENCE
Category: order
Opcode: 0x0FAEF0
CPU: P4+
Tested by: t3415 t4140

IisMFENCE:: PROC
    IiRequire 686,SSE2
    IiEmitOpcode 0x0F,0xAE,0xF0
    IiDispatchFormat none
.none:RET
 ENDP IisMFENCE::

↑ SFENCE: Store Fence
Description: SFENCE
Category: order
Opcode: 0x0FAEF8
CPU: P3+
Tested by: t3415 t4140

IisSFENCE:: PROC
    IiRequire 686,SSE1
    IiEmitOpcode 0x0F,0xAE,0xF8
    IiDispatchFormat none
.none:RET
 ENDP IisSFENCE::

↑ PAUSE: Spin Loop Hint
Description: PAUSE
Category: cachect
Opcode: 0xF390
CPU: P4+
Tested by: t3415 t4140

IisPAUSE:: PROC
    IiRequire 686,SSE2
    IiEmitOpcode 0xF3,0x90
    IiDispatchFormat none
.none:RET
 ENDP IisPAUSE::

↑ ARPL: Adjust RPL Field of Segment Selector
Description: ARPL
Category: system
Operands: Ew,Gw
Opcode: 0x63 /r
Flags: modified:....Z..., defined:....Z...
CPU: 286+
Tested by: t3403

IisARPL:: PROC
    IiAbortIf64
    IiRequire 286,PROT
    IiEncoding DATA=WORD
    IiEmitOpcode 0x63
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat r16.r16, mem.r16:
.mem.r16:
.r16.r16:
    RET
 ENDP IisARPL::

↑ CLTS: Clear Task-Switched Flag in CR0
Description: CLTS
Category: system
Operands: CR0
Opcode: 0x0F06
CPU: 02+
Tested by: t3403

IisCLTS:: PROC
    IiRequire 286,PRIV
    IiEmitOpcode 0x0F,0x06
    IiDispatchFormat none
.none:RET
 ENDP IisCLTS::

↑ INVD: Invalidate Internal Caches
Description: INVD
Category: system
Opcode: 0x0F08
CPU: 04+
Tested by: t3403

IisINVD:: PROC
    IiRequire 486,PRIV
    IiEmitOpcode 0x0F,0x08
    IiDispatchFormat none
.none:RET
 ENDP IisINVD::

↑ INVLPG: Invalidate TLB Entry
Description: INVLPG
Category: system
Operands: M
Opcode: 0x0F01 /7
CPU: 04+
Tested by: t3403

IisINVLPG:: PROC
    IiRequire 486,PRIV
    IiEmitOpcode 0x0F,0x01
    IiOpEn M
    IiModRM /7
    IiDispatchFormat mem
.mem:RET
 ENDP IisINVLPG::

↑ LAR: Load Access Rights Byte
Description: LAR
Category: system
Operands: Gvqp,Mw | Gvqp,Rv
Opcode: 0x0F02 /r | 0x0F02 /r
Flags: modified:....Z..., defined:....Z...
CPU: 02+
Tested by: t3406

IisLAR:: PROC
    MOV CL,0x02 ; Secondary opcode.
.op:IiRequire 286,PROT
    IiEncoding DATA=WORD
    IiDataSize Operand1, SpecifyMem=OFF
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat \
       r16.mem,r16.r16,r16.r32,r16.r64,\
       r32.mem,r32.r16,r32.r32,r32.r64,\
       r64.mem,r64.r16,r64.r32,r64.r64
.r16.mem:
.r16.r16:
.r16.r32:
.r16.r64:
.r32.mem:
.r32.r16:
.r32.r32:
.r32.r64:
.r64.mem:
.r64.r16:
.r64.r32:
.r64.r64
    RET
 ENDP IisLAR::

↑ LSL: Load Segment Limit
Description: LSL
Category: system
Operands: Gvqp,Mw | Gvqp,Rv
Opcode: 0x0F03 /r | 0x0F03 /r
Flags: modified:....Z..., defined:....Z...
CPU: 02+
Tested by: t3406

IisLSL:: PROC
    MOV CL,0x03 ; Secondary opcode.
    JMP IisLAR.op:
 ENDP IisLSL::

↑ LMSW: Load Machine Status Word
Description: LMSW
Category: system
Operands: MSW,Ew
Opcode: 0x0F01 /6
CPU: 02+
Tested by: t3421

IisLMSW:: PROC
     IiRequire 286,PRIV
     IiModRM /6
.ld: IiEncoding DATA=WORD ; Width of memory operand is always 16 bits.
     IiEmitOpcode 0x0F,0x01
     IiOpEn M
     IiDispatchFormat r16, r32, r64, mem
.mem:
.r64:
.r32:
.r16:
     RET
 ENDP IisLMSW::

↑ SMSW: Store Machine Status Word
Description: SMSW
Category: system
Operands: Mw,MSW | Rvqp,MSW
Opcode: 0x0F01 /4 | 0x0F01 /4
CPU: 02+
Documented: D²¹
Tested by: t3421

IisSMSW:: PROC
     IiRequire 086
     IiModRM /4
     CMP DL,mem
     JE IisLMSW.ld:
     IiDataSize Operand1
     JMP IisLMSW.ld:
 ENDP IisSMSW::

↑ RDMSR: Read from Model Specific Register
Description: RDMSR
Category: system
Operands: rAX,rDX,rCX,MSR
Opcode: 0x0F32
CPU: P1+
Tested by: t3418

IisRDMSR:: PROC
    IiRequire 586,PRIV
    IiEmitOpcode 0x0F,0x32
    IiDispatchFormat none
.none:RET
 ENDP IisRDMSR::

↑ WRMSR: Write to Model Specific Register
Description: WRMSR
Category: system
Operands: MSR,rCX,rAX,rDX
Opcode: 0x0F30
CPU: P1+
Tested by: t3418

IisWRMSR:: PROC
    IiRequire 586,PRIV
    IiEmitOpcode 0x0F,0x30
    IiDispatchFormat none
.none:RET
 ENDP IisWRMSR::

↑ RDTSC: Read Time-Stamp Counter
Description: RDTSC
Category: system
Operands: EAX,EDX,I...
Opcode: 0x0F31
CPU: P1+
Tested by: t3418

IisRDTSC:: PROC
    IiRequire 586
    IiEmitOpcode 0x0F,0x31
    IiDispatchFormat none
.none:RET
 ENDP IisRDTSC::

↑ RDTSCP: Read Time-Stamp Counter and Processor ID
Description: RDTSCP
Category: system
Operands: EAX,EDX,ECX,...
Opcode: 0x0F01F9
CPU: C7+
Tested by: t3418

IisRDTSCP:: PROC
    IiRequire 686
    IiEmitOpcode 0x0F,0x01,0xF9
    IiDispatchFormat none
.none:RET
 ENDP IisRDTSCP::

↑ RSM: Resume from System Management Mode
Description: RSM
Category: system,branch
Operands: Fw
Opcode: 0x0FAA
CPU: 03++
Tested by: t3418 t4205

IisRSM:: PROC
    IiRequire 586,PRIV
    IiEmitOpcode 0x0F,0xAA
    IiDispatchFormat none
.none:RET
 ENDP IisRSM::

↑ RDRAND: Read Random Number
Description: RDRAND
Operands: reg
Opcode: 0x0FC7 /6
Documented: Intel
Tested by: t3418

IisRDRAND:: PROC
    IiRequire 686, SPEC
    IiEmitOpcode 0x0F,0xC7
    IiDataSize Operand1
    IiOpEn M
    IiModRM /6
    IiDispatchFormat r16, r32, r64
.r64:
.r32:
.r16:
    RET
 ENDP IisRDRAND::

↑ LGDT: Load Global Descriptor Table Register
Description: LGDT
Category: system
Operands: GDTR,Ms
Opcode: 0x0F01 /2
CPU: 02+
Tested by: t3409

IisLGDT:: PROC
     IiModRM /2
.pv: IiRequire PRIV
.np: IiRequire 286  ; Entry for non-privileged instructions.
     IiOpEn M
     IiEmitOpcode 0x0F,0x01
     IiDispatchFormat mem
.mem:RET
 ENDP IisLGDT::

↑ LIDT: Load Interrupt Descriptor Table Register
Description: LIDT
Category: system
Operands: IDTR,Ms
Opcode: 0x0F01 /3
CPU: 02+
Tested by: t3409

IisLIDT:: PROC
    IiModRM /3
    JMP IisLGDT.pv:
 ENDP IisLIDT::

↑ SGDT: Store Global Descriptor Table Register
Description: SGDT
Category: system
Operands: Ms,GDTR
Opcode: 0x0F01 /0
CPU: 02+
Tested by: t3409

IisSGDT:: PROC
    IiModRM /0
    JMP IisLGDT.np:
 ENDP IisSGDT::

↑ SIDT: Store Interrupt Descriptor Table Register
Description: SIDT
Category: system
Operands: Ms,IDTR
Opcode: 0x0F01 /1
CPU: 02+
Tested by: t3409

IisSIDT:: PROC
    IiModRM /1
    JMP IisLGDT.np:
 ENDP IisSIDT::

↑ SLDT: Store Local Descriptor Table Register
Description: SLDT
Category: system
Operands: Mw,LDTR | Rvqp,LDTR
Opcode: 0x0F00 /0 | 0x0F00 /0
CPU: 02+
Tested by: t3412

IisSLDT:: PROC
     IiModRM /0
 .rm:IiRequire 286
     IiEmitOpcode 0x0F,0x00
     IiEncoding DATA=WORD
     IiOpEn M
     IiDispatchFormat r16, r32, r64, mem
.r64:
.r32:
.r16:IiDataSize Operand1, SpecifyMem=OFF
.mem:RET
 ENDP IisSLDT::

↑ STR: Store Task Register
Description: STR
Category: system
Operands: Mw,TR | Rvqp,TR
Opcode: 0x0F00 /1 | 0x0F00 /1
CPU: 02+
Tested by: t3412

IisSTR:: PROC
    IiModRM /1
    JMP IisSLDT.rm:
 ENDP IisSTR::

↑ LLDT: Load Local Descriptor Table Register
Description: LLDT
Category: system
Operands: LDTR,Ew
Opcode: 0x0F00 /2
CPU: 02+
Tested by: t3412

IisLLDT:: PROC
    IiModRM /2
    IiRequire PRIV
.rm:IiRequire 286,PROT
    IiEncoding DATA=WORD
    IiEmitOpcode 0x0F,0x00
    IiOpEn M
    IiDispatchFormat r16, r32, r64, mem
.r64:
.r32:
.r16:
.mem:RET
 ENDP IisLLDT::

↑ LTR: Load Task Register
Description: LTR
Category: system
Operands: TR,Ew
Opcode: 0x0F00 /3
CPU: 02+
Tested by: t3412

IisLTR:: PROC
    IiModRM /3
    IiRequire PRIV
    JMP IisLLDT.rm:
 ENDP IisLTR::

↑ VERR: Verify a Segment for Reading
Description: VERR
Category: system
Operands: Ew
Opcode: 0x0F00 /4
Flags: modified:....Z..., defined:....Z...
CPU: 02+
Tested by: t3433

IisVERR:: PROC
    IiModRM /4
    JMP IisLLDT.rm:
 ENDP IisVERR::

↑ VERW: Verify a Segment for Writing
Description: VERW
Category: system
Operands: Ew
Opcode: 0x0F00 /5
Flags: modified:....Z..., defined:....Z...
CPU: 02+
Tested by: t3433

IisVERW:: PROC
    IiModRM /5
    JMP IisLLDT.rm:
 ENDP IisVERW::

↑ SYSCALL: Fast System Call
Description: SYSCALL
Category: system,branch
Operands: RCX,R11,SS,...
Opcode: 0x0F05
CPU: P4+
Documented: D²³
See also: LOADALL286
Tested by: t3427

IisSYSCALL:: PROC
    MOV CL,0x05
.op:IiRequire 686
    IiEmitOpcode 0x0F,ECX
    IiDispatchFormat none
.none:RET
 ENDP IisSYSCALL::

↑ SYSRET: Return From Fast System Call
Description: SYSRET
Category: system,branch,trans
Operands: SS,Fd,R11,...
Opcode: 0x0F07
CPU: P4+
See also: LOADALL
Tested by: t3427

IisSYSRET:: PROC
    IiRequire PRIV
    MOV CL,0x07
    JMP IisSYSCALL.op:
 ENDP IisSYSRET::

↑ RDPMC: Read Performance-Monitoring Counters
Description: RDPMC
Category: system
Operands: EAX,EDX,PMC
Opcode: 0x0F33
CPU: PX+
Tested by: t3418 t3427

IisRDPMC:: PROC
    MOV CL,0x33
    JMP IisSYSCALL.op:
 ENDP IisRDPMC::

↑ SYSENTER: Fast System Call
Description: SYSENTER
Category: system,branch
Operands: SS,ESP,I...,... | SS,RSP,I...,...
Opcode: 0x0F34 ^Sr | 0x0F34 ^Sr
Flags: modified:..I....., defined:..I....., values:..I.....
CPU: P2+
Tested by: t3427

IisSYSENTER:: PROC
    MOV CL,0x34
    JMP IisSYSCALL.op:
 ENDP IisSYSENTER::

↑ SYSEXIT: Fast Return from Fast System Call
Description: SYSEXIT
Category: system,branch,trans
Operands: SS,eSP,I...,...
Opcode: 0x0F35 ^Sr
CPU: P2+
Documented: D²⁹
Tested by: t3427

IisSYSEXIT:: PROC
    IiRequire PRIV
    MOV CL,0x35
    JMP IisSYSCALL.op:
 ENDP IisSYSEXIT::

↑ GETSEC: GETSEC Leaf Functions
Category: smx
Operands: EAX
Opcode: 0x0F37
CPU: C2++
Documented: D³⁰
See also: WRSHR (same opcode)
Tested by: t3427

IisGETSEC:: PROC
    MOV CL,0x37
    JMP IisSYSCALL.op:
 ENDP IisGETSEC::

↑ WBINVD: Write Back and Invalidate Cache
Description: WBINVD
Category: system
Opcode: 0x0F09
CPU: 04+
Tested by: t3403

IisWBINVD:: PROC
    IiRequire 486,PRIV
    IiEmitOpcode 0x0F,0x09
    IiDispatchFormat none
.none:RET
 ENDP IisWBINVD::

↑ UD0: Undefined Instruction
Category: system, undoc
Opcode: 0x0FFF
Documented: Cyrix, AMD
Tested by: t3424

IisUD0:: PROC
    IiRequire 186,UNDOC
    IiEmitOpcode 0x0F,0xFF
    IiDispatchFormat none
.none:RET
 ENDP IisUD0::

↑ UD1: Undefined Instruction
Operands: system, undoc
Opcode: 0x0FB9
Documented: X86_instruction_listings
Tested by: t3424

IisUD1:: PROC
    IiRequire 186,UNDOC
    IiEmitOpcode 0x0F,0xB9
    IiDispatchFormat none
.none:RET
 ENDP IisUD1::

↑ UD2: Undefined Instruction
Description: UD2
Category: gen,control
Opcode: 0x0F0B
CPU: 02+
Documented: Intel
Tested by: t3424

IisUD2:: PROC
    IiRequire 186
    IiEmitOpcode 0x0F,0x0B
    IiDispatchFormat none
.none:RET
 ENDP IisUD2::

↑ UD2A: Undefined Instruction
Operands: -
Opcode: 0x0F0B
CPU: 186
Tested by: t3424

IisUD2A:: PROC
    JMP IisUD2
 ENDP IisUD2A::

↑ UD2B: Undefined Instruction
Operands: -
Opcode: 0x0FB9
CPU: 186
Tested by: t3424

IisUD2B:: PROC
    JMP IisUD1
 ENDP IisUD2B::

↑ CLFLUSH: Flush Cache Line
Description: CLFLUSH
Category: sse2,cachect
Operands: Mb
Opcode: 0x0FAE /7
CPU: P4+
Tested by: t3436

IisCLFLUSH:: PROC
     IiRequire SSE2
     IiEmitOpcode 0x0F,0xAE
     IiOpEn M
     IiModRM /7
     IiDispatchFormat mem
.mem:RET
 ENDP IisCLFLUSH::

↑ LOADALL286: Load system data from address 80h:0 .. 80h:66h
Category: system, undoc
Operands: -
Opcode: 0x0F05
CPU: 286 only
Documented: Wikipedia, rcollings.org
See also: SYSCALL
Tested by: t3439

IisLOADALL286:: PROC
    IiRequire 286,UNDOC
    IiEmitOpcode 0x0F,0x05
    IiDispatchFormat none
.none:RET
 ENDP IisLOADALL286::

↑ LOADALL: Load All of the CPU Registers from ES:EDI
Category: system, undoc
Operands: -
Opcode: 0x0F07
CPU: 386
Documented: U ²² Wikipedia, rcollings.org
See also: SYSRET
Tested by: t3439

IisLOADALL:: PROC
    IiRequire 386,UNDOC
    IiEmitOpcode 0x0F,0x07
    IiDispatchFormat none
.none:RET
 ENDP IisLOADALL::

↑ PREFETCH: Prefetch L1 Data-Cache Line
Category: system, AMD
Operands: mem
Opcode: 0x0F0D /0
CPU: 586
Tested by: t3430

IisPREFETCH:: PROC
     IiModRM /0
.rm: IiRequire 586,D3NOW,AMD
     IiEmitOpcode 0x0F,0x0D
     IiOpEn M
     IiDispatchFormat mem
.mem:RET
 ENDP IisPREFETCH::

↑ PREFETCHW: Prefetch Data into Caches in Anticipation of a Write
Description: PREFETCHW
Category: system
Operands: mem
Opcode: 0x0F0D /1
CPU: 586
Tested by: t3430

IisPREFETCHW:: PROC
     IiModRM /1
     JMP IisPREFETCH.rm:
 ENDP IisPREFETCHW::

↑ PREFETCHWT1: Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
Description: PREFETCHWT1
Category: system, undoc
Operands: mem
CPU: 686
Documented: felixcloutier.com
Tested by: t3430

IisPREFETCHWT1:: PROC
     IiRequire 686,UNDOC
     IiModRM /2
     JMP IisPREFETCH.rm:
 ENDP IisPREFETCHWT1::

↑ PREFETCHNTA: Prefetch Data Into Caches
Category: sse1,fetch
Operands: Mb
Opcode: 0x0F18 /0
CPU: P3+
Tested by: t3430

IisPREFETCHNTA:: PROC
     IiModRM /0
.rm: IiRequire 686
     IiOpEn M
     IiEmitOpcode 0x0F,0x18
     IiDispatchFormat mem
.mem:RET
 ENDP IisPREFETCHNTA::

↑ PREFETCHT0: Prefetch Data Into Caches
Category: sse1,fetch
Operands: Mb
Opcode: 0x0F18 /1
CPU: P3+
Tested by: t3430

IisPREFETCHT0:: PROC
     IiModRM /1
     JMP IisPREFETCHNTA.rm:
 ENDP IisPREFETCHT0::

↑ PREFETCHT1: Prefetch Data Into Caches
Category: sse1,fetch
Operands: Mb
Opcode: 0x0F18 /2
CPU: P3+
Tested by: t3430

IisPREFETCHT1:: PROC
     IiModRM /2
     JMP IisPREFETCHNTA.rm:
 ENDP IisPREFETCHT1::

↑ PREFETCHT2: Prefetch Data Into Caches
Category: sse1,fetch
Operands: Mb
Opcode: 0x0F18 /3
CPU: P3+
Tested by: t3430

IisPREFETCHT2:: PROC
     IiModRM /3
     JMP IisPREFETCHNTA.rm:
 ENDP IisPREFETCHT2::

↑ SWAPGS: Swap GS Base Register
Description: SWAPGS
Category: system
Operands: GS,I...
Opcode: 0x0F01F8
CPU: P4+
Tested by: t3436

IisSWAPGS:: PROC
    IiRequire X64,PRIV
    IiAbortIfNot64
    IiEmitOpcode 0x0F,0x01,0xF8
    IiDispatchFormat none
.none:RET
 ENDP IisSWAPGS::

↑ JMPE: Jump to IA-64 Instruction Set
Category: system,branch
Operands: r/m16 | r/m32 | imm16/imm32
Opcode: 0x0F00 /6 | 0x0FB8 imm
CPU: IT+
See also: JMP, IitXBEGIN.
Tested by: t3155 t3156 t3157
Invokes: IiRelocSizeRIP

IisJMPE:: PROC
     IiRequire X64,UNDOC
     IiAllowModifier DIST,ADDR,DATA
     IiEncoding DIST=NEAR
     IiEmitOpcode 0x0F
     CMP DL,imm
     JE .imm:
     IiDataSize Operand1, UseSegment=ON
     IiDispatchFormat r16,r32,r64,m16,m32,m64
.m64:
.r64:IiDispatchWidth BITS64=.m16:
     IiAbort '6735' ; Required operand width 16 of this instruction cannot be used in 64bit mode.
.m16:
.r16:
.m32:
.r32:
     IiEmitOpcode 0x00
     IiOpEn M
     IiModRM /6
     RET
.imm:IiEmitOpcode 0xB8
     IiAllowModifier IMM
.rel::MOV EAX,[EDI+II.Operand1+EXP.Low]     ; Also entry point for IitXBEGIN.
     MOV EDX,[EDI+II.Operand1+EXP.High]
     MOV [EDI+II.ImmLow],EAX
     MOV [EDI+II.ImmHigh],EDX
     MOV EAX,[EDI+II.Operand1+EXP.Sym]
     MOV EDX,[EBX+STM.Section] ; Current section.
     MOV [EDI+II.ImmRelocSym],EAX
     MOV EBP,[EDI+II.Operand1+EXP.Seg] ; Target segment.
     MOV EAX,[EDX+SSS.SegmPtr] ; Segment of the current JMPE instruction.
     MOV [EDI+II.ImmRelocSeg],EBP
     CMP EBP,EAX
     MOV EAX,iiRelocImmRIP
     JE .Im: ; If EBP=EAX, use intrasegment call, no RELOC record.
     MOV EAX,iiRelocImmRel ; Otherwise encode immediate as relocable value.
.Im: SetSt [EDI+II.Reloc],EAX ; Set type of relocation.
     Invoke IiRelocSizeRIP::,EDI,EBX ; Inspect Imm-RIP magnitude and set iiMfgIMM_Mask to EAX.
     IiDispatchWidth BITS32=.Im.32:, BITS64=.Im.64:
.Im.16:JSt [EDI+II.MfgExplicit],iiMfgIMM_DWORD|iiMfgDATA_DWORD,.Ipr: ; Prolong on explicit request.
     JSt EAX,iiMfgIMM_DWORD,.Ipr: ; Prolong when distance is not word-encodable.
.ImW:SetSt [EDI+II.MfgEmitted],iiMfgDIST_NEAR+iiMfgADDR_REL+iiMfgDATA_WORD+iiMfgIMM_WORD ; Use 16bit near jump.
     RET
.Ipr:IiEmitPrefix OTOGGLE
.ImD:SetSt [EDI+II.MfgEmitted],iiMfgDIST_NEAR+iiMfgADDR_REL+iiMfgDATA_DWORD+iiMfgIMM_DWORD ; Use 32bit near jump.
     RET
.Im.32:JNSt [EDI+II.MfgExplicit],iiMfgIMM_WORD|iiMfgDATA_WORD,.ImD:
     JSt EAX,iiMfgIMM_DWORD,.ImD: ; Though explicitly requested IMM=WORD, the distance is above 64K.
     IiEmitPrefix OTOGGLE
     JMP .ImW:
.Im.64:SetSt [EDI+II.MfgEmitted],iiMfgDIST_NEAR+iiMfgADDR_REL+iiMfgIMM_DWORD+iiMfgDATA_QWORD
     RET
 ENDP IisJMPE::

↑ HCF: Halt and Catch Fire
Category: UNDOC
Opcode: 0xF00FC7C8
CPU: PENT
Documented: saylor.org
See also: CMPXCHG8B
Tested by: t3403

IisHCF:: PROC
    IiRequire UNDOC
    IiEmitPrefix LOCK
    IiEmitOpcode 0x0F,0xC7,0xC8
    IiDispatchFormat none
.none:RET
  ENDP IisHCF::

↑ BNDLDX: Loading bounds register from memory
Category: MPX
Operands: bndreg,mem
Opcode: 0x0F1A /r
Tested by: t4315

IisBNDLDX:: PROC
    MOV CL,0x1A
.op:IiRequire MPX
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat bnd.mem
.bnd.mem:RET
 ENDP IisBNDLDX::

↑ BNDLDX: Saving bound pair for bounds register
Category: MPX
Operands: bndreg, mem
Opcode: 0xF30F1B /r
Tested by: t4310

IisBNDMK:: PROC
    IiEmitPrefix REPE
    MOV CL,0x1B
    JMP IisBNDLDX.op:
 ENDP IisBNDMK::

↑ BNDSTX: Saving bounds register to memory
Category: MPX
Operands: mem,bndreg
Opcode: 0x0F1B /r
Tested by: t4315

IisBNDSTX:: PROC
    IiRequire MPX
    IiEmitOpcode 0x0F,0x1B
    IiOpEn MR
    IiModRM /r
    IiDispatchFormat mem.bnd
.mem.bnd:RET
 ENDP IisBNDSTX::

↑ BNDCL: Checking lower bound with bounds register lower value and operands
Category: MPX
Operands: bndreg,r/mem
Opcode: 0xF30F1A /r
Tested by: t4310

IisBNDCL:: PROC
    IiEmitPrefix REPE
    MOV CL,0x1A
.op:IiRequire MPX
    IiEmitOpcode 0x0F,ECX
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat bnd.mem,bnd.r32,bnd.r64
.bnd.mem:
.bnd.r32:
.bnd.r64:
    RET
 ENDP IisBNDCL::

↑ BNDCU: Checking upper bound with bounds register upper value and operands
Category: MPX
Operands: bndreg,r/mem
Opcode: 0xF20F1A /r
Tested by: t4310

IisBNDCU:: PROC
    MOV CL,0x1A
.op:IiEmitPrefix REPNE
    JMP IisBNDCL.op:
 ENDP IisBNDCU::

↑ BNDCN: Checking upper bound with bounds register upper value and operands
Category: MPX
Operands: bndreg,r/mem
Opcode: 0xF20F1B /r
Tested by: t4310

IisBNDCN:: PROC
    MOV CL,0x1B
    JMP IisBNDCU.op:
 ENDP IisBNDCN::

↑ BNDMOV: Accessing bounds register
Category: MPX
Operands: bndreg,bndreg/mem || bndreg/mem, bndreg
Opcode: 0x660F1A /r || 0x660F1B /r
Tested by: t4315

IisBNDMOV:: PROC
    IiRequire MPX
    IiAllowModifier CODE
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F
    IiModRM /r
    IiDispatchFormat bnd.mem, mem.bnd, bnd.bnd
.mem.bnd:
    IiEncoding CODE=LONG
    IiEmitOpcode 0x1B
    IiOpEn MR
    RET
.bnd.bnd:
    IiDispatchCode LONG=.mem.bnd:
.bnd.mem:
    IiEncoding CODE=SHORT
    IiEmitOpcode 0x1A
    IiOpEn RM
    RET
 ENDP IisBNDMOV::

↑ ENCLU: Execute an Enclave User Function of Specified Leaf Number
Category: SGX
Operands: implicit EAX
Opcode: 0x0F01D7
Tested by: t4330

IisENCLU:: PROC
    IiRequire PRIV, SGX
    IiEmitOpcode 0x0F,0x01,0xD7
    IiDispatchFormat none 
.none:RET
  ENDP IisENCLU::

↑ ENCLS: Execute an Enclave System Function of Specified Leaf Number
Category: SGX
Operands: implicit EAX
Opcode: 0x0F01CF
Tested by: t4330

IisENCLS:: PROC
    IiRequire PRIV,SGX
    IiEmitOpcode 0x0F,0x01,0xCF
    IiDispatchFormat none 
.none:RET
 ENDP IisENCLS::

↑ CLAC: CLear Access prevention Control flag
Description: CLAC
Operands: -
Opcode: 0x0F01CA
Tested by: t4330

IisCLAC:: PROC
    IiRequire 686, SPEC
    IiEmitOpcode 0x0F,0x01,0xCA
    IiDispatchFormat none 
.none:RET
 ENDP IisCLAC::

↑ STAC: SeT Access prevention Control flag
Description: STAC
Operands: -
Opcode: 0x0F01CB
Tested by: t4330

IisSTAC:: PROC
    IiRequire 686, SPEC
    IiEmitOpcode 0x0F,0x01,0xCB
    IiDispatchFormat none 
.none:RET
 ENDP IisSTAC::

↑ RDPKRU: ReaD Protection Keys Register
Operands: -
Opcode: 0x0F01EE
CPU: 686
Tested by: t4330

IisRDPKRU:: PROC
    IiRequire X64
    IiAbortIfNot64
    IiEmitOpcode 0x0F,0x01,0xEE
    IiDispatchFormat none 
.none:RET
 ENDP IisRDPKRU::

↑ WRPKRU: WRite Protection Keys Register
Operands: -
Opcode: 0x0F01EF
CPU: 686
Tested by: t4330

IisWRPKRU:: PROC
    IiRequire X64
    IiAbortIfNot64
    IiEmitOpcode 0x0F,0x01,0xEF
    IiDispatchFormat none 
.none:RET
 ENDP IisWRPKRU::

↑ IBTS: IBTS base,bitoffset,len,src
Category: Deprecated
Operands: r/m16,AX,CL,r16 || r/m32,EAX,CL,r32
Opcode: 0x0FA7 /r
Flags: none
CPU: 386 CPU stepping attribute of “A0” through “B0” only
Documented: [ObsoleteBTS]
Tested by: t3220

IisIBTS:: PROC
    IiRequire 386,UNDOC
    IiEmitOpcode 0x0F,0xA7
    IiDataSize SpecifyMem=OFF
    IiOpEn MR
    IiModRM /r
    IiAbortIfNot Operand3,CL
    IiDispatchFormat r16.r16.r8.r16, mem.r16.r8.r16, \
                     r32.r32.r8.r32, mem.r32.r8.r32 
.r16.r16.r8.r16:
.mem.r16.r8.r16:                                                  
    IiAbortIfNot Operand2,AX
    IiSwap Operand2, Operand4
    RET
.r32.r32.r8.r32:
.mem.r32.r8.r32:
    IiAbortIfNot Operand2,EAX
    IiSwap Operand2, Operand4
    RET
 ENDP IisIBTS::

↑ XBTS: XBTS dst,base,bitoffset,len
Category: Deprecated
Operands: r16,r/m16,AX,CL || r32,r/m32,EAX,CL
Opcode: 0x0FA6 /r
Flags: none
CPU: 386 CPU stepping attribute of “A0” through “B0” only
Documented: [ObsoleteBTS]
Tested by: t3220

IisXBTS:: PROC
    IiRequire 386,UNDOC
    IiEmitOpcode 0x0F,0xA6
    IiDataSize SpecifyMem=OFF
    IiOpEn RM
    IiModRM /r
    IiAbortIfNot Operand4,CL
    IiDispatchFormat r16.r16.r16.r8, r16.mem.r16.r8, \
                     r32.r32.r32.r8, r32.mem.r32.r8 
.r16.r16.r16.r8:
.r16.mem.r16.r8:
    IiAbortIfNot Operand3,AX
    RET
.r32.r32.r32.r8:
.r32.mem.r32.r8:    
    IiAbortIfNot Operand3,EAX
    RET
 ENDP IisXBTS::

↑ CLZERO: Zero 64byte cacheline
Operands: implicit [RAX]
Opcode: 0x0FAEF8
CPU: 686
Tested by: t3436

IisCLZERO:: PROC
    IiRequire 686,AMD
    IiEmitOpcode 0x0F,0x01,0xFC
    IiDispatchFormat none
.none:RET
 ENDP IisCLZERO::

↑ CLFLUSHOPT: Optimized cacheline flush
Operands: mem
Opcode: 0x660FAE /7
CPU: 686
Tested by: t3436

IisCLFLUSHOPT:: PROC
    IiRequire 686
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xAE
    IiOpEn M
    IiModRM /7
    IiDispatchFormat mem
.mem:RET
 ENDP IisCLFLUSHOPT::

↑ RDSEED: Generate random number
Description: RDSEED
Operands: reg
Opcode: 0x0FC7 /7
Tested by: t3418

IisRDSEED:: PROC
    IiRequire 686, SPEC
    IiEmitOpcode 0x0F,0xC7
    IiOpEn M
    IiModRM /7
    IiDataSize
    IiDispatchFormat r16,r32,r64
.r64:
.r32:
.r16:
     RET
 ENDP IisRDSEED::

↑ CL1INVMB: Invalidate L1 cache data with MPBT tag
Operands: -
Opcode: 0x0F0A
CPU: 48-core SCC
Documented: intel.com
Tested by: t3421

IisCL1INVMB:: PROC
    IiRequire 686,SPEC
    IiEmitOpcode 0x0F,0x0A
    IiDispatchFormat none
.none:RET
 ENDP IisCL1INVMB::

↑ ALTINST: Switch to alternate (not x86) instruction set
Category: VIA
Operands: -
Opcode: 0x0F3F
CPU: VIA
Documented: ANTAUR datasheet
Tested by: t3421

IisALTINST:: PROC
    IiRequire VIA,SPEC
    IiEmitOpcode 0x0F,0x3F
    IiDispatchFormat none
.none:RET
  ENDP IisALTINST::

↑ HINT_NOP: Hintable No Operation
Category: gen,control
Operands: Ordinal, mem
Opcode: 0x0F18 /0 || .. || 0x0F1F /7
CPU: PP-P2
Documented: M²⁵
Tested by: t4142

IisHINT_NOP:: PROC
    IiRequire 686,UNDOC
    IiDataSize Operand2
    MOV EAX,[EDI+II.Operand1+EXP.Low] ; Ordinal 0..63.
    MOV ECX,EAX
    CMP ECX,63
    IiAbort cc=A,'6531' ; 1st operand of HINT_NOP may not exceed 63 (00q..77q).
    SHR EAX,3
    SHL ECX,28
    ADD AL,0x18
    AND ECX,iiPpgModDigit
    SetSt ECX,iiPpgModRMd
    IiEmitOpcode 0x0F,EAX
    IiOpEn VM ; Operand1 is actually ignored in ModRM.
    IiModRM ECX
    IiDispatchFormat imm.r16,imm.r32,imm.r64,imm.m16,imm.m32,imm.m64
.imm.r16:
.imm.r32:
.imm.r64:
.imm.m16:
.imm.m32:
.imm.m64:
    RET
 ENDP IisHINT_NOP::

↑ HINT_NOPW: Hintable No Operation, WORD
Category: gen,control
Operands: Ordinal, mem
Opcode: 0x0F18 /0 || .. || 0x0F1F /7
CPU: PP-P2
Documented: M²⁵
Tested by: t4142

IisHINT_NOPW:: PROC
    IiSuffixed HINT_NOP,W, Category=s
 ENDP IisHINT_NOPW::

↑ HINT_NOPD: Hintable No Operation, DWORD
Category: gen,control
Operands: Ordinal, mem
Opcode: 0x0F18 /0 || .. || 0x0F1F /7
CPU: PP-P2
Documented: M²⁵
Tested by: t4142

IisHINT_NOPD:: PROC
    IiSuffixed HINT_NOP,D, Category=s
 ENDP IisHINT_NOPD::

↑ HINT_NOPQ: Hintable No Operation, QWORD
Category: gen,control
Operands: Ordinal, mem
Opcode: 0x0F18 /0 || .. || 0x0F1F /7
CPU: PP-P2
Documented: M²⁵
Tested by: t4142

IisHINT_NOPQ:: PROC
    IiSuffixed HINT_NOP,Q, Category=s
 ENDP IisHINT_NOPQ::

↑ NOP: No Operation
Description: NOP
Category: gen,control
Operands: | Ev | Ev
Opcode: 0x90 | 0x0F0D | 0x0F1F /0
Documented: D³
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP:: PROC
      IiAllowModifier DATA
      IiDispatchFormat none, r16, r32, r64, mem
.none:IiEmitOpcode 0x90
      RET
.r16:
.r32:
.r64:
.mem:
    IiRequire 686
    IiDataSize Operand1,UseSegment=ON,SpecifyMem=OFF
    IiEmitOpcode 0x0F,0x1F
    IiOpEn M
    IiModRM /0
    RET
 ENDP IisNOP::

↑ NOP1: No operation 1 byte
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP1:: PROC
      IiEmitOpcode 0x90 ; XCHG rAX,rAX
      IiDispatchFormat none
.none:RET
 ENDP IisNOP1::

↑ NOP2: No operation 2 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP2:: PROC
      IiDispatchFormat none
.none:IiEncoding DATA=WORD
      IiDispatchWidth BITS16=.16:
.386: IiEmitOpcode 0x66,0x90
      RET
.16:  IiDispatchCPU CPU_386=.386:
      IiEmitOpcode 0x87,0xC9
      RET
    RET
 ENDP IisNOP2::

↑ NOP3: No operation 3 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP3:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiEncoding DATA=WORD
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x90,0x87,0xC9
      RET
.686: IiEmitOpcode 0x66,0x67,0x90
      RET
.64:  IiEmitOpcode 0x0F,0x1F,0x00
      IiEncoding DATA=DWORD,ADDR=ABS,
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x8D,0x40,0x00
      IiEncoding DATA=DWORD,ADDR=ABS,
      RET
 ENDP IisNOP3::

↑ NOP4: No operation 4 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP4:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiEncoding DATA=WORD
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x87,0xC9,0x87,0xD2
      RET
.686: IiEmitOpcode 0x67,0x0F,0x1F,0x00
      IiEncoding DATA=WORD,ADDR=ABS
      RET
.64:  IiEmitOpcode 0x0F,0x1F,0x40
      IiEncoding DATA=DWORD,ADDR=ABS,DISP=BYTE
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x8D,0x44,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
 ENDP IisNOP4::

↑ NOP5: No operation 5 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP5:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiEncoding DATA=WORD
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x90,0x87,0xC9,0x87,0xD2
      RET
.686: IiEmitOpcode 0x67,0x0F,0x1F,0x40
      IiEncoding DATA=WORD,ADDR=ABS,DISP=BYTE
      RET
.64:  IiEmitOpcode 0x0F,0x1F,0x44,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x3E,0x8D,0x44,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
 ENDP IisNOP5::

↑ NOP6: No operation 6 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP6:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiEncoding DATA=WORD
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x87,0xC9,0x87,0xD2,0x87,0xDB
      RET
.686: IiEmitOpcode 0x67,0x0F,0x1F,0x44,0x20
      IiEncoding DATA=WORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
.64:  IiEmitOpcode 0x66,0x0F,0x1F,0x44,0x20
      IiEncoding DATA=WORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x8D,0x80
      IiEncoding DATA=DWORD,ADDR=ABS,DISP=DWORD
      RET
 ENDP IisNOP6::

↑ NOP7: No operation 7 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP7:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x90,0x87,0xC9,0x87,0xD2,0x87,0xDB
      IiEncoding DATA=WORD
      RET
.686: IiEmitOpcode 0x66,0x67,0x0F,0x1F,0x44,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=BYTE
      RET
.64:  IiEmitOpcode 0x0F,0x1F,0x80
      IiEncoding DATA=DWORD,ADDR=ABS,DISP=DWORD
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x8D,0x84,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET
 ENDP IisNOP7::

↑ NOP8: No operation 8 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP8:: PROC
      IiDispatchFormat none 
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x87,0xC9,0x87,0xD2,0x87,0xDB,0x87,0xE4
      IiEncoding DATA=WORD
      RET
.686: IiEmitOpcode 0x67,0x0F,0x1F,0x80
      IiEncoding DATA=DWORD,ADDR=ABS,DISP=DWORD
      RET
.64:  IiEmitOpcode 0x0F,0x1F,0x84,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x3E,0x8D,0x84,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET 
 ENDP IisNOP8::

↑ NOP9: No operation 9 bytes
See also: No-operation encoding.
Tested by: t3131 t3132 t3133

IisNOP9:: PROC
      IiDispatchFormat none
.none:IiDispatchWidth BITS64=.64:, BITS32=.32:
      IiDispatchCPU  CPU_686=.686:
      IiEmitOpcode 0x90,0x87,0xC9,0x87,0xD2,0x87,0xDB,0x87,0xE4
      IiEncoding DATA=WORD
      RET
.686: IiEmitOpcode 0x67,0x0F,0x1F,0x84,0x20
      IiEncoding DATA=DWORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET
.64:  IiEmitOpcode 0x66,0x0F,0x1F,0x84,0x20
      IiEncoding DATA=WORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET
.32:  IiDispatchCPU CPU_686=.64:
      IiEmitOpcode 0x66,0x3E,0x8D,0x84,0x20
      IiEncoding DATA=WORD,SCALE=VERBATIM,ADDR=ABS,DISP=DWORD
      RET
 ENDP IisNOP9::

↑ SAVEPREVSSP: Save Previous Shadow Stack Pointer
Description: SAVEPREVSSP
Opcode: 0xF30F01EA
See also: RSTORSSP.

IisSAVEPREVSSP:: PROC
      IiRequire 686
      IiDispatchFormat none
.none:IiEmitOpcode 0xF3,0x0F,0x01,0xEA
      RET
 ENDP IisSAVEPREVSSP::

↑ RSTORSSP: Save Previous Shadow Stack Pointer
Description: RSTORSSP
Opcode: 0xF30F01 /5
See also: SAVEPREVSSP.

IisRSTORSSP:: PROC
      IiRequire 686
      IiEmitOpcode 0xF3,0x0F,0x01
      IiModRM  /5
      IiOpEn M
      IiDispatchFormat mem
.mem: RET
 ENDP IisRSTORSSP::

↑ SETSSBSY: Mark Shadow Stack Busy
Description: SETSSBSY
Opcode: 0xF30F01E8

IisSETSSBSY:: PROC
      IiRequire 686
      IiEmitOpcode 0xF3,0x0F,0x01,0xE8
      IiDispatchFormat none
.none:RET
 ENDP IisSETSSBSY::

↑ CLRSSBSY: Clear Busy Flag in a Supervisor Shadow Stack Token
Description: CLRSSBSY
Opcode: 0xF30FAE /6

IisCLRSSBSY:: PROC
      IiRequire 686
      IiEmitOpcode 0xF3,0x0F,0xAE
      IiModRM  /5
      IiOpEn M
      IiDispatchFormat mem
.mem: RET
 ENDP IisCLRSSBSY::

↑ INCSSPD: Increment Shadow Stack Pointer by 4*r32[7:0]
Description: INCSSPD
Opcode: 0xF30FAE /5

IisINCSSPD:: PROC
      IiRequire 686
      IiEmitOpcode 0xF3,0x0F,0xAE
      IiModRM  /5
      IiOpEn M
      IiDispatchFormat r32
.r32: RET
 ENDP IisINCSSPD::

↑ INCSSPQ: Increment Shadow Stack Pointer by 8*r64[7:0]
Description: INCSSPQ
Opcode: 0xF30FAE /6

IisINCSSPQ:: PROC
      IiRequire X64
      IiEmitOpcode 0xF3,0x48,0x0F,0xAE
      IiModRM  /5
      IiOpEn M
      IiDispatchFormat r64
.r64: RET
 ENDP IisINCSSPQ::

↑ ENCLV: Execute an Enclave VMM Function of Specified Leaf Number
Description: ENCLV
Opcode: 0x0F01C0

IisENCLV:: PROC
      IiRequire 686
      IiEmitOpcode 0x0F,0x01,0x0C
      IiDispatchFormat none
.none:RET
 ENDP IisENCLV::

↑ ENDBR32: Terminate an Indirect Branch in 32-bit and Compatibility Mode
Description: ENDBR32
Opcode: 0xF30F1EFB

IisENDBR32:: PROC
      IiRequire 686,CET
      IiEmitOpcode 0xF3,0x0F,0x1E,0xFB
      IiDispatchFormat none
.none:RET
 ENDP IisENDBR32::

↑ ENDBR64: Terminate an Indirect Branch in 64-bit Mode
Description: ENDBR64
Opcode: 0xF30F1EFA

IisENDBR64:: PROC
      IiRequire X64,CET
      IiEmitOpcode 0xF3,0x0F,0x1E,0xFA
      IiDispatchFormat none
.none:RET
 ENDP IisENDBR64::

↑ HRESET: History Reset
Description: HRESET
Opcode: 0xF30F3AF0C

IisHRESET:: PROC
      IiRequire 686,PRIV
      IiEmitOpcode 0xF3,0x0F,0x3A,0xF0,0xC0
;      IiModRM /r
;      IiOpEn M
      IiDispatchFormat none
.none:RET
 ENDP IisHRESET::

↑ SENDUIPI: Send User Interprocessor Interrupt
Description: SENDUIPI
Opcode: 0xF30FC7 /6

IisSENDUIPI:: PROC
      IiRequire X64,PRIV
      IiEmitOpcode 0xF3,0x0F,0xC7
      IiModRM /6
      IiOpEn M
      IiDispatchFormat r64
.r64: RET
 ENDP IisSENDUIPI::

↑ SERIALIZE: Serialize Instruction Execution
Description: SERIALIZE
Opcode: 0x0F01E8

IisSERIALIZE:: PROC
      IiRequire 686
      IiEmitOpcode 0x0F,0x01,0xE8
      IiDispatchFormat none
.none:RET
 ENDP IisSERIALIZE::

↑ UMONITOR: User Level Set Up Monitor Address
Description: UMONITOR
Opcode: 0xF30FAE /6

IisUMONITOR:: PROC
      IiEmitOpcode 0xF3,0x0F,0xAE
      IiModRM /6
      IiOpEn M
      IiDispatchFormat r16,r32,r64
.r16:
.r32:
.r64:
      RET
 ENDP IisUMONITOR::

↑ UMWAIT: User Level Monitor Wait
Description: UMWAIT
Opcode: 0xF20FAE /6

IisUMWAIT:: PROC
      IiRequire 686
      IiEmitOpcode 0xF2,0x0F,0xAE
      IiModRM /6
      IiOpEn M
      IiDispatchFormat r32
.r32: RET
 ENDP IisUMWAIT::

  ENDPROGRAM iis

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