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Test t5416: Machine instructions VFNMADD132PD VFNMADD213PD VFNMADD231PD VFNMSUB132PD VFNMSUB213PD VFNMSUB231PD

Tested procedures

IibVFNMADD132PD   IibVFNMADD213PD   IibVFNMADD231PD   IibVFNMSUB132PD   IibVFNMSUB213PD   IibVFNMSUB231PD  

Source & expected listing t5416.htm.lst

| | EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=34,DUMPALL=OFF,CPU=X64,SIMD=AVX512,FMA=ON,EVEX=ON, MVEX=ON | |t5416 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF |[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE |00000000:C4E2E99CCB | VFNMADD132PD XMM1,XMM2,XMM3 |00000005:C4E2E99C4D40 | VFNMADD132PD XMM1,XMM2,[RBP+40h] |0000000B:62F2ED0C9C4D04<4 | VFNMADD132PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000012:62F2ED189C4D08<3 | VFNMADD132PD XMM1,XMM2,[RBP+40h],BCST=ON |00000019:C4E2ED9CCB | VFNMADD132PD YMM1,YMM2,YMM3 |0000001E:C4E2ED9C4D40 | VFNMADD132PD YMM1,YMM2,[RBP+40h] |00000024:62F2EDAC9C4D02<5 | VFNMADD132PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000002B:62F2ED389C4D08<3 | VFNMADD132PD YMM1,YMM2,[RBP+40h],BCST=ON |00000032:62F2ED489CCB | VFNMADD132PD ZMM1,ZMM2,ZMM3 |00000038:62F2ED789CCB | VFNMADD132PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000003E:62F2E91C9CCB | VFNMADD132PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000044:62F2E99C9CCB | VFNMADD132PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000004A:62F2ED489C4D01<6 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h] |00000051:62F2EDCC9C4D01<6 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000058:62F2ED589C4D08<3 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h],BCST=ON |0000005F:62F2E9089C4D01<6 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |00000066:62F2E9189C4D08<3 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |0000006D:62F2E9289C4D02<5 | VFNMADD132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |00000074:C4E2E9ACCB | VFNMADD213PD XMM1,XMM2,XMM3 |00000079:C4E2E9AC4D40 | VFNMADD213PD XMM1,XMM2,[RBP+40h] |0000007F:62F2ED0CAC4D04<4 | VFNMADD213PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000086:62F2ED18AC4D08<3 | VFNMADD213PD XMM1,XMM2,[RBP+40h],BCST=ON |0000008D:C4E2EDACCB | VFNMADD213PD YMM1,YMM2,YMM3 |00000092:C4E2EDAC4D40 | VFNMADD213PD YMM1,YMM2,[RBP+40h] |00000098:62F2EDACAC4D02<5 | VFNMADD213PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000009F:62F2ED38AC4D08<3 | VFNMADD213PD YMM1,YMM2,[RBP+40h],BCST=ON |000000A6:62F2ED48ACCB | VFNMADD213PD ZMM1,ZMM2,ZMM3 |000000AC:62F2ED78ACCB | VFNMADD213PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |000000B2:62F2E91CACCB | VFNMADD213PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |000000B8:62F2E99CACCB | VFNMADD213PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |000000BE:62F2ED48AC4D01<6 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h] |000000C5:62F2EDCCAC4D01<6 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |000000CC:62F2ED58AC4D08<3 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000000D3:62F2E908AC4D01<6 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000000DA:62F2E918AC4D08<3 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000000E1:62F2E928AC4D02<5 | VFNMADD213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |000000E8:C4E2E9BCCB | VFNMADD231PD XMM1,XMM2,XMM3 |000000ED:C4E2E9BC4D40 | VFNMADD231PD XMM1,XMM2,[RBP+40h] |000000F3:62F2ED0CBC4D04<4 | VFNMADD231PD XMM1,XMM2,[RBP+40h],MASK=K4 |000000FA:62F2ED18BC4D08<3 | VFNMADD231PD XMM1,XMM2,[RBP+40h],BCST=ON |00000101:C4E2EDBCCB | VFNMADD231PD YMM1,YMM2,YMM3 |00000106:C4E2EDBC4D40 | VFNMADD231PD YMM1,YMM2,[RBP+40h] |0000010C:62F2EDACBC4D02<5 | VFNMADD231PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000113:62F2ED38BC4D08<3 | VFNMADD231PD YMM1,YMM2,[RBP+40h],BCST=ON |0000011A:62F2ED48BCCB | VFNMADD231PD ZMM1,ZMM2,ZMM3 |00000120:62F2ED78BCCB | VFNMADD231PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |00000126:62F2E91CBCCB | VFNMADD231PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |0000012C:62F2E99CBCCB | VFNMADD231PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |00000132:62F2ED48BC4D01<6 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h] |00000139:62F2EDCCBC4D01<6 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000140:62F2ED58BC4D08<3 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h],BCST=ON |00000147:62F2E908BC4D01<6 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |0000014E:62F2E918BC4D08<3 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |00000155:62F2E928BC4D02<5 | VFNMADD231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |0000015C:C4E2E99ECB | VFNMSUB132PD XMM1,XMM2,XMM3 |00000161:C4E2E99E4D40 | VFNMSUB132PD XMM1,XMM2,[RBP+40h] |00000167:62F2ED0C9E4D04<4 | VFNMSUB132PD XMM1,XMM2,[RBP+40h],MASK=K4 |0000016E:62F2ED189E4D08<3 | VFNMSUB132PD XMM1,XMM2,[RBP+40h],BCST=ON |00000175:C4E2ED9ECB | VFNMSUB132PD YMM1,YMM2,YMM3 |0000017A:C4E2ED9E4D40 | VFNMSUB132PD YMM1,YMM2,[RBP+40h] |00000180:62F2EDAC9E4D02<5 | VFNMSUB132PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000187:62F2ED389E4D08<3 | VFNMSUB132PD YMM1,YMM2,[RBP+40h],BCST=ON |0000018E:62F2ED489ECB | VFNMSUB132PD ZMM1,ZMM2,ZMM3 |00000194:62F2ED789ECB | VFNMSUB132PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000019A:62F2E91C9ECB | VFNMSUB132PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |000001A0:62F2E99C9ECB | VFNMSUB132PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |000001A6:62F2ED489E4D01<6 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h] |000001AD:62F2EDCC9E4D01<6 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |000001B4:62F2ED589E4D08<3 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000001BB:62F2E9089E4D01<6 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000001C2:62F2E9189E4D08<3 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000001C9:62F2E9289E4D02<5 | VFNMSUB132PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |000001D0:C4E2E9AECB | VFNMSUB213PD XMM1,XMM2,XMM3 |000001D5:C4E2E9AE4D40 | VFNMSUB213PD XMM1,XMM2,[RBP+40h] |000001DB:62F2ED0CAE4D04<4 | VFNMSUB213PD XMM1,XMM2,[RBP+40h],MASK=K4 |000001E2:62F2ED18AE4D08<3 | VFNMSUB213PD XMM1,XMM2,[RBP+40h],BCST=ON |000001E9:C4E2EDAECB | VFNMSUB213PD YMM1,YMM2,YMM3 |000001EE:C4E2EDAE4D40 | VFNMSUB213PD YMM1,YMM2,[RBP+40h] |000001F4:62F2EDACAE4D02<5 | VFNMSUB213PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |000001FB:62F2ED38AE4D08<3 | VFNMSUB213PD YMM1,YMM2,[RBP+40h],BCST=ON |00000202:62F2ED48AECB | VFNMSUB213PD ZMM1,ZMM2,ZMM3 |00000208:62F2ED78AECB | VFNMSUB213PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000020E:62F2E91CAECB | VFNMSUB213PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000214:62F2E99CAECB | VFNMSUB213PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000021A:62F2ED48AE4D01<6 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h] |00000221:62F2EDCCAE4D01<6 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000228:62F2ED58AE4D08<3 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h],BCST=ON |0000022F:62F2E908AE4D01<6 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |00000236:62F2E918AE4D08<3 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |0000023D:62F2E928AE4D02<5 | VFNMSUB213PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |00000244:C4E2E9BECB | VFNMSUB231PD XMM1,XMM2,XMM3 |00000249:C4E2E9BE4D40 | VFNMSUB231PD XMM1,XMM2,[RBP+40h] |0000024F:62F2ED0CBE4D04<4 | VFNMSUB231PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000256:62F2ED18BE4D08<3 | VFNMSUB231PD XMM1,XMM2,[RBP+40h],BCST=ON |0000025D:C4E2EDBECB | VFNMSUB231PD YMM1,YMM2,YMM3 |00000262:C4E2EDBE4D40 | VFNMSUB231PD YMM1,YMM2,[RBP+40h] |00000268:62F2EDACBE4D02<5 | VFNMSUB231PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000026F:62F2ED38BE4D08<3 | VFNMSUB231PD YMM1,YMM2,[RBP+40h],BCST=ON |00000276:62F2ED48BECB | VFNMSUB231PD ZMM1,ZMM2,ZMM3 |0000027C:62F2ED78BECB | VFNMSUB231PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |00000282:62F2E91CBECB | VFNMSUB231PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000288:62F2E99CBECB | VFNMSUB231PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000028E:62F2ED48BE4D01<6 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h] |00000295:62F2EDCCBE4D01<6 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000029C:62F2ED58BE4D08<3 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000002A3:62F2E908BE4D01<6 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000002AA:62F2E918BE4D08<3 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000002B1:62F2E928BE4D02<5 | VFNMSUB231PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. | |ENDPROGRAM t5416

Expected messages t5416.out

I0180 Assembling source file "t5416.htm". I0270 Assembling source "t5416". I0310 Assembling source pass 1. I0330 Assembling source pass 2 - final. I0470 Assembling program "t5416". "t5416.htm"{64} I0510 Assembling program pass 1. "t5416.htm"{64} I0530 Assembling program pass 2 - final. "t5416.htm"{64} I0660 16bit TINY BIN file "t5416.bin" created, size=696. "t5416.htm"{174} I0650 Program "t5416" assembled in 2 passes with errorlevel 0. "t5416.htm"{174} I0750 Source "t5416" (192 lines) assembled in 2 passes with errorlevel 0. I0860 Listing file "t5416.htm.lst" created, size=9111. I0990 EuroAssembler terminated with errorlevel 0.