Test t5413:
Machine instructions VFNMADD312PS VFNMADD123PS VFNMADD321PS VFNMSUB312PS VFNMSUB123PS VFNMSUB321PS
- Tested procedures
-
IibVFNMADD312PS
IibVFNMADD123PS
IibVFNMADD321PS
IibVFNMSUB312PS
IibVFNMSUB123PS
IibVFNMSUB321PS
- Source & expected listing
t5413.htm.lst
-
| | EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=34,DUMPALL=OFF,CPU=X64,SIMD=AVX512,FMA=ON,EVEX=ON, MVEX=ON
| |t5413 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF
|[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE
|00000000:C4E2699CCB | VFNMADD312PS XMM1,XMM2,XMM3
|00000005:C4E2699C4D40 | VFNMADD312PS XMM1,XMM2,[RBP+40h]
|0000000B:62F26D0C9C4D04<4 | VFNMADD312PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000012:62F26D189C4D10<2 | VFNMADD312PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000019:C4E26D9CCB | VFNMADD312PS YMM1,YMM2,YMM3
|0000001E:C4E26D9C4D40 | VFNMADD312PS YMM1,YMM2,[RBP+40h]
|00000024:62F26DAC9C4D02<5 | VFNMADD312PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000002B:62F26D389C4D10<2 | VFNMADD312PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000032:62F26D489CCB | VFNMADD312PS ZMM1,ZMM2,ZMM3
|00000038:62F26D789CCB | VFNMADD312PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000003E:62F2691C9CCB | VFNMADD312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000044:62F2699C9CCB | VFNMADD312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000004A:62F26D489C4D01<6 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h]
|00000051:62F26DCC9C4D01<6 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000058:62F26D589C4D10<2 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000005F:62F269089C4D01<6 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000066:62F269189C4D10<2 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000006D:62F269289C4D04<4 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000074:62F269389C4D02<5 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000007B:62F269489C4D04<4 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000082:62F269689C4D02<5 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000089:62F269789C4D02<5 | VFNMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000090:C4E269ACCB | VFNMADD123PS XMM1,XMM2,XMM3
|00000095:C4E269AC4D40 | VFNMADD123PS XMM1,XMM2,[RBP+40h]
|0000009B:62F26D0CAC4D04<4 | VFNMADD123PS XMM1,XMM2,[RBP+40h],MASK=K4
|000000A2:62F26D18AC4D10<2 | VFNMADD123PS XMM1,XMM2,[RBP+40h],BCST=ON
|000000A9:C4E26DACCB | VFNMADD123PS YMM1,YMM2,YMM3
|000000AE:C4E26DAC4D40 | VFNMADD123PS YMM1,YMM2,[RBP+40h]
|000000B4:62F26DACAC4D02<5 | VFNMADD123PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000000BB:62F26D38AC4D10<2 | VFNMADD123PS YMM1,YMM2,[RBP+40h],BCST=ON
|000000C2:62F26D48ACCB | VFNMADD123PS ZMM1,ZMM2,ZMM3
|000000C8:62F26D78ACCB | VFNMADD123PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|000000CE:62F2691CACCB | VFNMADD123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|000000D4:62F2699CACCB | VFNMADD123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|000000DA:62F26D48AC4D01<6 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h]
|000000E1:62F26DCCAC4D01<6 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000000E8:62F26D58AC4D10<2 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|000000EF:62F26908AC4D01<6 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|000000F6:62F26918AC4D10<2 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|000000FD:62F26928AC4D04<4 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000104:62F26938AC4D02<5 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000010B:62F26948AC4D04<4 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000112:62F26968AC4D02<5 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000119:62F26978AC4D02<5 | VFNMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000120:C4E269BCCB | VFNMADD321PS XMM1,XMM2,XMM3
|00000125:C4E269BC4D40 | VFNMADD321PS XMM1,XMM2,[RBP+40h]
|0000012B:62F26D0CBC4D04<4 | VFNMADD321PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000132:62F26D18BC4D10<2 | VFNMADD321PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000139:C4E26DBCCB | VFNMADD321PS YMM1,YMM2,YMM3
|0000013E:C4E26DBC4D40 | VFNMADD321PS YMM1,YMM2,[RBP+40h]
|00000144:62F26DACBC4D02<5 | VFNMADD321PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000014B:62F26D38BC4D10<2 | VFNMADD321PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000152:62F26D48BCCB | VFNMADD321PS ZMM1,ZMM2,ZMM3
|00000158:62F26D78BCCB | VFNMADD321PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000015E:62F2691CBCCB | VFNMADD321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000164:62F2699CBCCB | VFNMADD321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000016A:62F26D48BC4D01<6 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h]
|00000171:62F26DCCBC4D01<6 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000178:62F26D58BC4D10<2 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000017F:62F26908BC4D01<6 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000186:62F26918BC4D10<2 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000018D:62F26928BC4D04<4 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000194:62F26938BC4D02<5 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000019B:62F26948BC4D04<4 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|000001A2:62F26968BC4D02<5 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|000001A9:62F26978BC4D02<5 | VFNMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|000001B0:C4E2699ECB | VFNMSUB312PS XMM1,XMM2,XMM3
|000001B5:C4E2699E4D40 | VFNMSUB312PS XMM1,XMM2,[RBP+40h]
|000001BB:62F26D0C9E4D04<4 | VFNMSUB312PS XMM1,XMM2,[RBP+40h],MASK=K4
|000001C2:62F26D189E4D10<2 | VFNMSUB312PS XMM1,XMM2,[RBP+40h],BCST=ON
|000001C9:C4E26D9ECB | VFNMSUB312PS YMM1,YMM2,YMM3
|000001CE:C4E26D9E4D40 | VFNMSUB312PS YMM1,YMM2,[RBP+40h]
|000001D4:62F26DAC9E4D02<5 | VFNMSUB312PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000001DB:62F26D389E4D10<2 | VFNMSUB312PS YMM1,YMM2,[RBP+40h],BCST=ON
|000001E2:62F26D489ECB | VFNMSUB312PS ZMM1,ZMM2,ZMM3
|000001E8:62F26D789ECB | VFNMSUB312PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|000001EE:62F2691C9ECB | VFNMSUB312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|000001F4:62F2699C9ECB | VFNMSUB312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|000001FA:62F26D489E4D01<6 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h]
|00000201:62F26DCC9E4D01<6 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000208:62F26D589E4D10<2 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000020F:62F269089E4D01<6 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000216:62F269189E4D10<2 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000021D:62F269289E4D04<4 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000224:62F269389E4D02<5 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000022B:62F269489E4D04<4 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000232:62F269689E4D02<5 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000239:62F269789E4D02<5 | VFNMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000240:C4E269AECB | VFNMSUB123PS XMM1,XMM2,XMM3
|00000245:C4E269AE4D40 | VFNMSUB123PS XMM1,XMM2,[RBP+40h]
|0000024B:62F26D0CAE4D04<4 | VFNMSUB123PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000252:62F26D18AE4D10<2 | VFNMSUB123PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000259:C4E26DAECB | VFNMSUB123PS YMM1,YMM2,YMM3
|0000025E:C4E26DAE4D40 | VFNMSUB123PS YMM1,YMM2,[RBP+40h]
|00000264:62F26DACAE4D02<5 | VFNMSUB123PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000026B:62F26D38AE4D10<2 | VFNMSUB123PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000272:62F26D48AECB | VFNMSUB123PS ZMM1,ZMM2,ZMM3
|00000278:62F26D78AECB | VFNMSUB123PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000027E:62F2691CAECB | VFNMSUB123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000284:62F2699CAECB | VFNMSUB123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000028A:62F26D48AE4D01<6 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h]
|00000291:62F26DCCAE4D01<6 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000298:62F26D58AE4D10<2 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000029F:62F26908AE4D01<6 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|000002A6:62F26918AE4D10<2 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|000002AD:62F26928AE4D04<4 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|000002B4:62F26938AE4D02<5 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|000002BB:62F26948AE4D04<4 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|000002C2:62F26968AE4D02<5 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|000002C9:62F26978AE4D02<5 | VFNMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|000002D0:C4E269BECB | VFNMSUB321PS XMM1,XMM2,XMM3
|000002D5:C4E269BE4D40 | VFNMSUB321PS XMM1,XMM2,[RBP+40h]
|000002DB:62F26D0CBE4D04<4 | VFNMSUB321PS XMM1,XMM2,[RBP+40h],MASK=K4
|000002E2:62F26D18BE4D10<2 | VFNMSUB321PS XMM1,XMM2,[RBP+40h],BCST=ON
|000002E9:C4E26DBECB | VFNMSUB321PS YMM1,YMM2,YMM3
|000002EE:C4E26DBE4D40 | VFNMSUB321PS YMM1,YMM2,[RBP+40h]
|000002F4:62F26DACBE4D02<5 | VFNMSUB321PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000002FB:62F26D38BE4D10<2 | VFNMSUB321PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000302:62F26D48BECB | VFNMSUB321PS ZMM1,ZMM2,ZMM3
|00000308:62F26D78BECB | VFNMSUB321PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000030E:62F2691CBECB | VFNMSUB321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000314:62F2699CBECB | VFNMSUB321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000031A:62F26D48BE4D01<6 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h]
|00000321:62F26DCCBE4D01<6 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000328:62F26D58BE4D10<2 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000032F:62F26908BE4D01<6 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000336:62F26918BE4D10<2 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000033D:62F26928BE4D04<4 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000344:62F26938BE4D02<5 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000034B:62F26948BE4D04<4 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000352:62F26968BE4D02<5 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000359:62F26978BE4D02<5 | VFNMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
| |ENDPROGRAM t5413
- Expected messages
t5413.out
I0180 Assembling source file "t5413.htm".
I0270 Assembling source "t5413".
I0310 Assembling source pass 1.
I0330 Assembling source pass 2 - final.
I0470 Assembling program "t5413". "t5413.htm"{64}
I0510 Assembling program pass 1. "t5413.htm"{64}
I0530 Assembling program pass 2 - final. "t5413.htm"{64}
I0660 16bit TINY BIN file "t5413.bin" created, size=864. "t5413.htm"{198}
I0650 Program "t5413" assembled in 2 passes with errorlevel 0. "t5413.htm"{198}
I0750 Source "t5413" (216 lines) assembled in 2 passes with errorlevel 0.
I0860 Listing file "t5413.htm.lst" created, size=11535.
I0990 EuroAssembler terminated with errorlevel 0.
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