Test t5411:
Machine instructions VFMADD312PS VFMADD123PS VFMADD321PS VFMSUB312PS VFMSUB123PS VFMSUB321PS
- Tested procedures
-
IibVFMADD312PS
IibVFMADD123PS
IibVFMADD321PS
IibVFMSUB312PS
IibVFMSUB123PS
IibVFMSUB321PS
- Source & expected listing
t5411.htm.lst
-
| | EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=34,DUMPALL=OFF,CPU=X64,SIMD=AVX512,FMA=ON,EVEX=ON, MVEX=ON
| |t5411 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF
|[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE
|00000000:C4E26998CB | VFMADD312PS XMM1,XMM2,XMM3
|00000005:C4E269984D40 | VFMADD312PS XMM1,XMM2,[RBP+40h]
|0000000B:62F26D0C984D04<4 | VFMADD312PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000012:62F26D18984D10<2 | VFMADD312PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000019:C4E26D98CB | VFMADD312PS YMM1,YMM2,YMM3
|0000001E:C4E26D984D40 | VFMADD312PS YMM1,YMM2,[RBP+40h]
|00000024:62F26DAC984D02<5 | VFMADD312PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000002B:62F26D38984D10<2 | VFMADD312PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000032:62F26D4898CB | VFMADD312PS ZMM1,ZMM2,ZMM3
|00000038:62F26D7898CB | VFMADD312PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000003E:62F2691C98CB | VFMADD312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000044:62F2699C98CB | VFMADD312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000004A:62F26D48984D01<6 | VFMADD312PS ZMM1,ZMM2,[RBP+40h]
|00000051:62F26DCC984D01<6 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000058:62F26D58984D10<2 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000005F:62F26908984D01<6 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000066:62F26918984D10<2 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000006D:62F26928984D04<4 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000074:62F26938984D02<5 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000007B:62F26948984D04<4 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000082:62F26968984D02<5 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000089:62F26978984D02<5 | VFMADD312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000090:C4E269A8CB | VFMADD123PS XMM1,XMM2,XMM3
|00000095:C4E269A84D40 | VFMADD123PS XMM1,XMM2,[RBP+40h]
|0000009B:62F26D0CA84D04<4 | VFMADD123PS XMM1,XMM2,[RBP+40h],MASK=K4
|000000A2:62F26D18A84D10<2 | VFMADD123PS XMM1,XMM2,[RBP+40h],BCST=ON
|000000A9:C4E26DA8CB | VFMADD123PS YMM1,YMM2,YMM3
|000000AE:C4E26DA84D40 | VFMADD123PS YMM1,YMM2,[RBP+40h]
|000000B4:62F26DACA84D02<5 | VFMADD123PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000000BB:62F26D38A84D10<2 | VFMADD123PS YMM1,YMM2,[RBP+40h],BCST=ON
|000000C2:62F26D48A8CB | VFMADD123PS ZMM1,ZMM2,ZMM3
|000000C8:62F26D78A8CB | VFMADD123PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|000000CE:62F2691CA8CB | VFMADD123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|000000D4:62F2699CA8CB | VFMADD123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|000000DA:62F26D48A84D01<6 | VFMADD123PS ZMM1,ZMM2,[RBP+40h]
|000000E1:62F26DCCA84D01<6 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000000E8:62F26D58A84D10<2 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|000000EF:62F26908A84D01<6 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|000000F6:62F26918A84D10<2 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|000000FD:62F26928A84D04<4 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000104:62F26938A84D02<5 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000010B:62F26948A84D04<4 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000112:62F26968A84D02<5 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000119:62F26978A84D02<5 | VFMADD123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000120:C4E269B8CB | VFMADD321PS XMM1,XMM2,XMM3
|00000125:C4E269B84D40 | VFMADD321PS XMM1,XMM2,[RBP+40h]
|0000012B:62F26D0CB84D04<4 | VFMADD321PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000132:62F26D18B84D10<2 | VFMADD321PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000139:C4E26DB8CB | VFMADD321PS YMM1,YMM2,YMM3
|0000013E:C4E26DB84D40 | VFMADD321PS YMM1,YMM2,[RBP+40h]
|00000144:62F26DACB84D02<5 | VFMADD321PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000014B:62F26D38B84D10<2 | VFMADD321PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000152:62F26D48B8CB | VFMADD321PS ZMM1,ZMM2,ZMM3
|00000158:62F26D78B8CB | VFMADD321PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000015E:62F2691CB8CB | VFMADD321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000164:62F2699CB8CB | VFMADD321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000016A:62F26D48B84D01<6 | VFMADD321PS ZMM1,ZMM2,[RBP+40h]
|00000171:62F26DCCB84D01<6 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000178:62F26D58B84D10<2 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000017F:62F26908B84D01<6 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000186:62F26918B84D10<2 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000018D:62F26928B84D04<4 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000194:62F26938B84D02<5 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000019B:62F26948B84D04<4 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|000001A2:62F26968B84D02<5 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|000001A9:62F26978B84D02<5 | VFMADD321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|000001B0:C4E2699ACB | VFMSUB312PS XMM1,XMM2,XMM3
|000001B5:C4E2699A4D40 | VFMSUB312PS XMM1,XMM2,[RBP+40h]
|000001BB:62F26D0C9A4D04<4 | VFMSUB312PS XMM1,XMM2,[RBP+40h],MASK=K4
|000001C2:62F26D189A4D10<2 | VFMSUB312PS XMM1,XMM2,[RBP+40h],BCST=ON
|000001C9:C4E26D9ACB | VFMSUB312PS YMM1,YMM2,YMM3
|000001CE:C4E26D9A4D40 | VFMSUB312PS YMM1,YMM2,[RBP+40h]
|000001D4:62F26DAC9A4D02<5 | VFMSUB312PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000001DB:62F26D389A4D10<2 | VFMSUB312PS YMM1,YMM2,[RBP+40h],BCST=ON
|000001E2:62F26D489ACB | VFMSUB312PS ZMM1,ZMM2,ZMM3
|000001E8:62F26D789ACB | VFMSUB312PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|000001EE:62F2691C9ACB | VFMSUB312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|000001F4:62F2699C9ACB | VFMSUB312PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|000001FA:62F26D489A4D01<6 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h]
|00000201:62F26DCC9A4D01<6 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000208:62F26D589A4D10<2 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000020F:62F269089A4D01<6 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000216:62F269189A4D10<2 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000021D:62F269289A4D04<4 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000224:62F269389A4D02<5 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000022B:62F269489A4D04<4 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000232:62F269689A4D02<5 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000239:62F269789A4D02<5 | VFMSUB312PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|00000240:C4E269AACB | VFMSUB123PS XMM1,XMM2,XMM3
|00000245:C4E269AA4D40 | VFMSUB123PS XMM1,XMM2,[RBP+40h]
|0000024B:62F26D0CAA4D04<4 | VFMSUB123PS XMM1,XMM2,[RBP+40h],MASK=K4
|00000252:62F26D18AA4D10<2 | VFMSUB123PS XMM1,XMM2,[RBP+40h],BCST=ON
|00000259:C4E26DAACB | VFMSUB123PS YMM1,YMM2,YMM3
|0000025E:C4E26DAA4D40 | VFMSUB123PS YMM1,YMM2,[RBP+40h]
|00000264:62F26DACAA4D02<5 | VFMSUB123PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|0000026B:62F26D38AA4D10<2 | VFMSUB123PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000272:62F26D48AACB | VFMSUB123PS ZMM1,ZMM2,ZMM3
|00000278:62F26D78AACB | VFMSUB123PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000027E:62F2691CAACB | VFMSUB123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000284:62F2699CAACB | VFMSUB123PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000028A:62F26D48AA4D01<6 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h]
|00000291:62F26DCCAA4D01<6 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000298:62F26D58AA4D10<2 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000029F:62F26908AA4D01<6 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|000002A6:62F26918AA4D10<2 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|000002AD:62F26928AA4D04<4 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|000002B4:62F26938AA4D02<5 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|000002BB:62F26948AA4D04<4 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|000002C2:62F26968AA4D02<5 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|000002C9:62F26978AA4D02<5 | VFMSUB123PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
|000002D0:C4E269BACB | VFMSUB321PS XMM1,XMM2,XMM3
|000002D5:C4E269BA4D40 | VFMSUB321PS XMM1,XMM2,[RBP+40h]
|000002DB:62F26D0CBA4D04<4 | VFMSUB321PS XMM1,XMM2,[RBP+40h],MASK=K4
|000002E2:62F26D18BA4D10<2 | VFMSUB321PS XMM1,XMM2,[RBP+40h],BCST=ON
|000002E9:C4E26DBACB | VFMSUB321PS YMM1,YMM2,YMM3
|000002EE:C4E26DBA4D40 | VFMSUB321PS YMM1,YMM2,[RBP+40h]
|000002F4:62F26DACBA4D02<5 | VFMSUB321PS YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON
|000002FB:62F26D38BA4D10<2 | VFMSUB321PS YMM1,YMM2,[RBP+40h],BCST=ON
|00000302:62F26D48BACB | VFMSUB321PS ZMM1,ZMM2,ZMM3
|00000308:62F26D78BACB | VFMSUB321PS ZMM1,ZMM2,ZMM3,ROUND=ZERO
|0000030E:62F2691CBACB | VFMSUB321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}.
|00000314:62F2699CBACB | VFMSUB321PS ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down.
|0000031A:62F26D48BA4D01<6 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h]
|00000321:62F26DCCBA4D01<6 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON
|00000328:62F26D58BA4D10<2 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],BCST=ON
|0000032F:62F26908BA4D01<6 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {16to16}.
|00000336:62F26918BA4D10<2 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to16}.
|0000033D:62F26928BA4D04<4 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to16}.
|00000344:62F26938BA4D02<5 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=3 ; {float16}.
|0000034B:62F26948BA4D04<4 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=4 ; {uint8}.
|00000352:62F26968BA4D02<5 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=6 ; {uint16}.
|00000359:62F26978BA4D02<5 | VFMSUB321PS ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=7 ; {sint16}.
| |ENDPROGRAM t5411
- Expected messages
t5411.out
I0180 Assembling source file "t5411.htm".
I0270 Assembling source "t5411".
I0310 Assembling source pass 1.
I0330 Assembling source pass 2 - final.
I0470 Assembling program "t5411". "t5411.htm"{64}
I0510 Assembling program pass 1. "t5411.htm"{64}
I0530 Assembling program pass 2 - final. "t5411.htm"{64}
I0660 16bit TINY BIN file "t5411.bin" created, size=864. "t5411.htm"{198}
I0650 Program "t5411" assembled in 2 passes with errorlevel 0. "t5411.htm"{198}
I0750 Source "t5411" (216 lines) assembled in 2 passes with errorlevel 0.
I0860 Listing file "t5411.htm.lst" created, size=11403.
I0990 EuroAssembler terminated with errorlevel 0.
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