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iiv.htm
Enumerations
IivList
Instruction handlers
ADCX ADOX BEXTR BLSI BLSMSK BLSR BZHI CLWB MULX PCOMMIT PDEP PEXT RDFSBASE RDGSBASE RORX SARX SHLX SHRX VPCLMULHQHQDQ VPCLMULHQLQDQ VPCLMULLQHQDQ VPCLMULLQLQDQ VPCLMULQDQ WRFSBASE WRGSBASE

IivHandlers
assemble AVX vector machine instructions.
See also
IiHandlers, [IntelVol2] [IntelAVX512]
iiv PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
 INCLUDEHEAD "euroasm.htm" ; Interface (structures, symbols and macros) of other modules.

iiv HEAD ; Start of module interface.
↑ %IivList
enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IivList requires the corresponding handler in this file.
See also
DictLookupIi
%IivList %SET \
BLSR, \
BLSMSK, \
BLSI, \
BZHI, \
BEXTR, \
ADCX, \
ADOX, \
RORX, \
SHLX, \
SARX, \
SHRX, \
PEXT, \
PDEP, \
MULX, \
VPCLMULQDQ, \
RDFSBASE, \
RDGSBASE, \
WRFSBASE, \
WRGSBASE, \
PCOMMIT, \
CLWB, \
VPCLMULLQLQDQ, \
VPCLMULHQLQDQ, \
VPCLMULLQHQDQ, \
VPCLMULHQHQDQ, \

;
  ENDHEAD iiv ; End of module interface.
↑ BLSR
Reset Lowest Set Bit
Description
BLSR
Intel reference
BLSR r32, r/m32 VEX.NDD.LZ.0F38.W0 F3 /1
BLSR r64, r/m64 VEX.NDD.LZ.0F38.W1 F3 /1
Opcode
0xF3
Tested by
t4410
IivBLSR:: PROC
    IiModRM /1
.rm:IiRequire ABM
    IiEmitOpcode 0xF3
    IiOpEn VM
    IiDispatchFormat  r32.r32, r32.mem, r64.r64, r64.mem
.r32.r32:
.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.NDD.LZ.0F38.W0
    RET
.r64.r64:
.r64.mem:
    IiEncoding DATA=QWORD
    IiEmitPrefix VEX.NDD.LZ.0F38.W1
    RET
  ENDP IivBLSR::
↑ BLSMSK
Get Mask Up to Lowest Set Bit
Description
BLSMSK
Intel reference
BLSMSK r32, r/m32 VEX.NDD.LZ.0F38.W0 F3 /2
BLSMSK r64, r/m64 VEX.NDD.LZ.0F38.W1 F3 /2
Opcode
0xF3
Tested by
t4410
IivBLSMSK:: PROC
    IiModRM /2
    JMP IivBLSR.rm:
  ENDP IivBLSMSK::
↑ BLSI
Extract Lowest Set Isolated Bit
Description
BLSI
Intel reference
BLSI r32, r/m32 VEX.NDD.LZ.0F38.W0 F3 /3
BLSI r64, r/m64 VEX.NDD.LZ.0F38.W1 F3 /3
Opcode
0xF3
Tested by
t4410
IivBLSI:: PROC
    IiModRM /3
    JMP IivBLSR.rm:
  ENDP IivBLSI::
↑ BZHI
Zero High Bits Starting with Specified Bit Position
Description
BZHI
Intel reference
BZHI r32a, r/m32, r32b VEX.NDS.LZ.0F38.W0 F5 /r
BZHI r64a, r/m64, r64b VEX.NDS.LZ.0F38.W1 F5 /r
Opcode
0xF5
Tested by
t4420
IivBZHI:: PROC
    IiEmitOpcode 0xF5
.op:IiRequire ABM
    IiOpEn RMV
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.mem.r32, r64.r64.r64, r64.mem.r64
.r32.r32.r32:
.r32.mem.r32:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.NDS.LZ.0F38.W0
    RET
.r64.r64.r64:
.r64.mem.r64:
    IiEncoding DATA=QWORD
    IiEmitPrefix VEX.NDS.LZ.0F38.W1
    RET
  ENDP IivBZHI::
↑ BEXTR
Bit Field Extract
Description
BEXTR
Intel reference
BEXTR r32a, r/m32, r32b VEX.NDS.LZ.0F38.W0 F7 /r
BEXTR r64a, r/m64, r64b VEX.NDS.LZ.0F38.W1 F7 /r
Opcode
0xF7
Tested by
t4420
IivBEXTR:: PROC
    IiEmitOpcode 0xF7
    JMP IivBZHI.op:
  ENDP IivBEXTR::
↑ ADCX
Unsigned Integer Addition of Two Operands with Carry Flag
Description
ADCX
Intel reference
ADCX r32, r/m32 66 0F 38 F6 /r
ADCX r64, r/m64 66 REX.w 0F 38 F6 /r
Opcode
0xF6
Tested by
t4420
IivADCX:: PROC
    IiEmitPrefix OTOGGLE
.pf:IiRequire SPEC
    IiEmitOpcode 0x0F,0x38,0xF6
    IiOpEn RM
    IiModRM /r
    IiDispatchFormat  r32.r32, r32.mem, r64.r64, r64.mem
.r32.r32:
.r32.mem:
    IiEncoding DATA=DWORD
    RET
.r64.r64:
.r64.mem:
    IiEncoding DATA=QWORD
    IiEmitPrefix REX.W
    RET
  ENDP IivADCX::
↑ ADOX
Unsigned Integer Addition of Two Operands with Overflow Flag
Description
ADOX
Intel reference
ADOX r32, r/m32 F3 0F 38 F6 /r
ADOX r64, r/m64 F3 REX.w 0F 38 F6 /r
Opcode
0xF6
Tested by
t4420
IivADOX:: PROC
    IiEmitPrefix REPE
    JMP IivADCX.pf:
  ENDP IivADOX::
↑ RORX
Rotate Right Logical Without Affecting Flags
Description
RORX
Intel reference
RORX r32, r/m32, imm8 VEX.LZ.F2.0F3A.W0 F0 /r ib
RORX r64, r/m64, imm8 VEX.LZ.F2.0F3A.W1 F0 /r ib
Opcode
0xF0
Tested by
t4422
IivRORX:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF0
    IiOpEn RM
    IiModRM /r
    IiEmitImm Operand3, BYTE
    IiDispatchFormat  r32.r32.imm, r32.mem.imm, r64.r64.imm, r64.mem.imm
.r32.r32.imm:
.r32.mem.imm:
    IiEmitPrefix VEX.LZ.F2.0F3A.W0
    RET
.r64.r64.imm:
.r64.mem.imm:
    IiEmitPrefix VEX.LZ.F2.0F3A.W1
    RET
  ENDP IivRORX::
↑ SHLX
Shift Logical Left Without Affecting Flags
Description
SHLX
Intel reference
SHLX r32a, r/m32, r32b VEX.NDS.LZ.66.0F38.W0 F7 /r
SHLX r64a, r/m64, r64b VEX.NDS.LZ.66.0F38.W1 F7 /r
Opcode
0xF7
Tested by
t4422
IivSHLX:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF7
    IiOpEn RMV
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.mem.r32, r64.r64.r64, r64.mem.r64
.r32.r32.r32:
.r32.mem.r32:
    IiEmitPrefix VEX.NDS.LZ.66.0F38.W0
    RET
.r64.r64.r64:
.r64.mem.r64:
    IiEmitPrefix VEX.NDS.LZ.66.0F38.W1
    RET
  ENDP IivSHLX::
↑ SARX
Shift Arithmetic Right Without Affecting Flags
Description
SARX
Intel reference
SARX r32a, r/m32, r32b VEX.NDS.LZ.F3.0F38.W0 F7 /r
SARX r64a, r/m64, r64b VEX.NDS.LZ.F3.0F38.W1 F7 /r
Opcode
0xF7
Tested by
t4422
IivSARX:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF7
    IiOpEn RMV
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.mem.r32, r64.r64.r64, r64.mem.r64
.r32.r32.r32:
.r32.mem.r32:
    IiEmitPrefix VEX.NDS.LZ.F3.0F38.W0
    RET
.r64.r64.r64:
.r64.mem.r64:
    IiEmitPrefix VEX.NDS.LZ.F3.0F38.W1
    RET
  ENDP IivSARX::
↑ SHRX
Shift Logical Right Without Affecting Flags
Description
SHRX
Intel reference
SHRX r32a, r/m32, r32b VEX.NDS.LZ.F2.0F38.W0 F7 /r
SHRX r64a, r/m64, r64b VEX.NDS.LZ.F2.0F38.W1 F7 /r
Opcode
0xF7
Tested by
t4422
IivSHRX:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF7
    IiOpEn RMV
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.mem.r32, r64.r64.r64, r64.mem.r64
.r32.r32.r32:
.r32.mem.r32:
    IiEmitPrefix VEX.NDS.LZ.F2.0F38.W0
    RET
.r64.r64.r64:
.r64.mem.r64:
    IiEmitPrefix VEX.NDS.LZ.F2.0F38.W1
    RET
  ENDP IivSHRX::
↑ PEXT
Parallel Bits Extract
Description
PEXT
Intel reference
PEXT r32a, r32b, r/m32 VEX.NDS.LZ.F3.0F38.W0 F5 /r
PEXT r64a, r64b, r/m64 VEX.NDS.LZ.F3.0F38.W1 F5 /r
Opcode
0xF5
Tested by
t4424
IivPEXT:: PROC
    IiRequire ABM 
    IiEmitOpcode 0xF5
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.r32.mem, r64.r64.r64, r64.r64.mem
.r32.r32.r32:
.r32.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.NDS.LZ.F3.0F38.W0
    RET
.r64.r64.r64:
.r64.r64.mem:
    IiEncoding DATA=QWORD
    IiEmitPrefix VEX.NDS.LZ.F3.0F38.W1
    RET
  ENDP IivPEXT::
↑ PDEP
Parallel Bits Deposit
Description
PDEP
Intel reference
PDEP r32a, r32b, r/m32 VEX.NDS.LZ.F2.0F38.W0 F5 /r
PDEP r64a, r64b, r/m64 VEX.NDS.LZ.F2.0F38.W1 F5 /r
Opcode
0xF5
Tested by
t4424
IivPDEP:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF5
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.r32.mem, r64.r64.r64, r64.r64.mem
.r32.r32.r32:
.r32.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.NDS.LZ.F2.0F38.W0
    RET
.r64.r64.r64:
.r64.r64.mem:
    IiEncoding DATA=QWORD
    IiEmitPrefix VEX.NDS.LZ.F2.0F38.W1
    RET
  ENDP IivPDEP::
↑ MULX
Unsigned Multiply by EDX/RDX Without Affecting Flags
Description
MULX
Intel reference
MULX r32a, r32b, r/m32 VEX.NDD.LZ.F2.0F38.W0 F6 /r
MULX r64a, r64b, r/m64 VEX.NDD.LZ.F2.0F38.W1 F6 /r
Comment
$euro;ASM tolerates implied rDX register as 4th operand.
Opcode
0xF6
Tested by
t4424
IivMULX:: PROC
    IiRequire ABM
    IiEmitOpcode 0xF6
    IiOpEn RVM
    IiModRM /r
    IiDispatchFormat  r32.r32.r32, r32.r32.mem, r64.r64.r64, r64.r64.mem, \
    r32.r32.r32.r32, r32.r32.mem.r32, r64.r64.r64.r64, r64.r64.mem.r64
.r32.r32.r32.r32:
.r32.r32.mem.r32:
    IiAbortIfNot Operand4,EDX
.r32.r32.r32:
.r32.r32.mem:
    IiEncoding DATA=DWORD
    IiEmitPrefix VEX.NDD.LZ.F2.0F38.W0
    RET
.r64.r64.r64.r64:
.r64.r64.mem.r64:
    IiAbortIfNot Operand4,RDX
.r64.r64.r64:
.r64.r64.mem:
    IiEncoding DATA=QWORD
    IiEmitPrefix VEX.NDD.LZ.F2.0F38.W1
    RET
  ENDP IivMULX::
↑ VPCLMULQDQ
Carry-Less Multiplication Quadword
Intel reference
VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8 VEX.NDS.128.66.0F3A.WIG 44 /r ib
Opcode
0x44
Tested by
t4426
IivVPCLMULQDQ:: PROC
    IiRequire SPEC
    IiEmitOpcode 0x44
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE, Max=17
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IivVPCLMULQDQ::
↑ VPCLMULLQLQDQ
Carry-Less Multiplication Qword imm=0x00
Intel reference
VPCLMULLQLQDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F3A.WIG 44 /r 00
Opcode
0x44
See also
VPCLMULQDQ.
Tested by
t4426
IivVPCLMULLQLQDQ:: PROC
    MOV CL,0x00
.im:IiImmCreate CL
    IiEmitOpcode 0x44
    IiOpEn RVM
    IiModRM /r
    IiEmitImm Operand4, BYTE
    IiEmitPrefix VEX.NDS.128.66.0F3A.WIG
    IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
    RET
  ENDP IivVPCLMULLQLQDQ::
↑ VPCLMULHQLQDQ
Carry-Less Multiplication Qword imm=0x01
Intel reference
VPCLMULHQLQDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F3A.WIG 44 /r 01
Opcode
0x44
See also
VPCLMULQDQ.
Tested by
t4426
IivVPCLMULHQLQDQ:: PROC
    MOV CL,0x01
    JMP IivVPCLMULLQLQDQ.im:
  ENDP IivVPCLMULHQLQDQ::
↑ VPCLMULLQHQDQ
Carry-Less Multiplication Qword imm=0x10
Intel reference
VPCLMULLQHQDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F3A.WIG 44 /r 10
Opcode
0x44
See also
VPCLMULQDQ.
Tested by
t4426
IivVPCLMULLQHQDQ:: PROC
    MOV CL,0x10
    JMP IivVPCLMULLQLQDQ.im:
  ENDP IivVPCLMULLQHQDQ::
↑ VPCLMULHQHQDQ
Carry-Less Multiplication Qword imm=0x11
Intel reference
VPCLMULHQHQDQ xmm1, xmm2, xmm3/m128 VEX.NDS.128.66.0F3A.WIG 44 /r 11
Opcode
0x44
See also
VPCLMULQDQ.
Tested by
t4426
IivVPCLMULHQHQDQ:: PROC
    MOV CL,0x11
    JMP IivVPCLMULLQLQDQ.im:
  ENDP IivVPCLMULHQHQDQ::
↑ RDFSBASE
Read FS Segment Base
Description
RDFSBASE
Intel reference
RDFSBASE r32 F3 0F AE /0
RDFSBASE r64 F3 REX.W 0F AE /0
Opcode
0xAE
Tested by
t3910
IivRDFSBASE:: PROC
     IiModRM /0
 .rm:IiAbortIfNot64
     IiOpEn M
     IiEmitPrefix REPE
     IiEmitOpcode 0x0F,0xAE
     IiDispatchFormat  r32, r64
.r32:IiEncoding DATA=DWORD
     RET
.r64:IiEncoding DATA=QWORD
     IiEmitPrefix REX.W
     RET
  ENDP IivRDFSBASE::
↑ RDGSBASE
Read GS Segment Base
Description
RDGSBASE
Intel reference
RDGSBASE r32 F3 0F AE /1
RDGSBASE r64 F3 REX.W 0F AE /1
Opcode
0xAE
Tested by
t3910
IivRDGSBASE:: PROC
    IiModRM /1
    JMP IivRDFSBASE.rm:
  ENDP IivRDGSBASE::
↑ WRFSBASE
Write FS Segment Base
Description
WRFSBASE
Intel reference
WRFSBASE r32 F3 0F AE /2
WRFSBASE r64 F3 REX.W 0F AE /2
Opcode
0xAE
Tested by
t3910
IivWRFSBASE:: PROC
    IiModRM /2
    JMP IivRDFSBASE.rm:
  ENDP IivWRFSBASE::
↑ WRGSBASE
Write GS Segment Base
Description
WRGSBASE
Intel reference
WRGSBASE r32 F3 0F AE /3
WRGSBASE r64 F3 REX.W 0F AE /3
Opcode
0xAE
Tested by
t3910
IivWRGSBASE:: PROC
    IiModRM /3
    JMP IivRDFSBASE.rm:
  ENDP IivWRGSBASE::
↑ PCOMMIT
Commits stores to persistent memory
Intel reference
PCOMMIT 66 0F AE F8
Opcode
0xAE
Tested by
t4142
IivPCOMMIT:: PROC
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xAE,0xF8
    IiDispatchFormat none
.none:RET
  ENDP IivPCOMMIT::
↑ CLWB
Cache Line Write Back
Intel reference
CLWB m8 66 0F AE /6
Opcode
0xAE
Tested by
t4142
IivCLWB:: PROC
    IiEmitPrefix OTOGGLE
    IiEmitOpcode 0x0F,0xAE
    IiOpEn M
    IiModRM /6
    IiDispatchFormat  mem
.mem:RET
  ENDP IivCLWB::
  ENDPROGRAM iiv

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