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iih.htm
Enumerations
IihList
Instruction handlers
VADDBF16
VADDPH
VADDSH
VBCSTNEBF162PS
VBCSTNESH2PS
VCMPBF16
VCMPPH
VCMPSH
VCOMISBF16
VCOMISH
VCOMXSD
VCOMXSH
VCOMXSS
VCVT2PH2BF8
VCVT2PH2BF8S
VCVT2PH2HF8
VCVT2PH2HF8S
VCVT2PS2PHX
VCVTBF162IBS
VCVTBF162IBS
VCVTBF162IUBS
VCVTBF162IUBS
VCVTBIASPH2BF8
VCVTBIASPH2BF8S
VCVTBIASPH2HF8
VCVTBIASPH2HF8S
VCVTDQ2PH
VCVTHF82PH
VCVTNE2PS2BF16
VCVTNEEBF162PS
VCVTNEEPH2PS
VCVTNEOBF162PS
VCVTNEOPH2PS
VCVTNEPS2BF16
VCVTPD2PH
VCVTPH2BF8
VCVTPH2BF8S
VCVTPH2DQ
VCVTPH2HF8
VCVTPH2HF8S
VCVTPH2IBS
VCVTPH2IUBS
VCVTPH2PD
VCVTPH2PSX
VCVTPH2QQ
VCVTPH2UDQ
VCVTPH2UQQ
VCVTPH2UW
VCVTPH2W
VCVTPH2IBS
VCVTPH2IUBS
VCVTPS2PHX
VCVTQQ2PH
VCVTSD2SH
VCVTSH2SD
VCVTSH2SI
VCVTSH2SS
VCVTSH2USI
VCVTSI2SH
VCVTSS2SH
VCVTSS2USI
VCVTBF162IBS
VCVTBF162IBS
VCVTBF162IUBS
VCVTBF162IUBS
VCVTTPD2DQS
VCVTTPD2QQS
VCVTTPD2UDQS
VCVTTPD2UQQS
VCVTTPH2DQ
VCVTTPH2IBS
VCVTTPH2IUBS
VCVTTPH2QQ
VCVTTPH2UDQ
VCVTTPH2UQQ
VCVTTPH2UW
VCVTTPH2W
VCVTTPS2DQS
VCVTTPH2IBS
VCVTTPH2IUBS
VCVTTPS2QQS
VCVTTPS2UDQS
VCVTTPS2UQQS
VCVTTSD2SIS
VCVTTSD2USIS
VCVTTSH2SI
VCVTTSH2USI
VCVTTSS2SIS
VCVTTSS2USIS
VCVTUDQ2PH
VCVTUQQ2PH
VCVTUSI2SH
VCVTUW2PH
VCVTW2PH
VDIVBF16
VDIVPH
VDIVSH
VDPBF16PS
VDPPHPS
VFCMADDCPH
VFCMADDCSH
VFCMULCPH
VFCMULCSH
VFMADD132BF16
VFMADD132PH
VFMADD132SH
VFMADD213BF16
VFMADD213PH
VFMADD213SH
VFMADD231BF16
VFMADD231PH
VFMADD231SH
VFMADDCPH
VFMADDCSH
VFMADDSUB132PS
VFMADDSUB213PS
VFMADDSUB231PS
VFMSUB132BF16
VFMSUB132PH
VFMSUB132SH
VFMSUB213BF16
VFMSUB213PH
VFMSUB213SH
VFMSUB231BF16
VFMSUB231PH
VFMSUB231SH
VFMSUBADD132PS
VFMSUBADD213PS
VFMSUBADD231PS
VFMULCPH
VFMULCSH
VFNMADD132BF16
VFNMADD132PH
VFNMADD132SH
VFNMADD213BF16
VFNMADD213PH
VFNMADD213SH
VFNMADD231BF16
VFNMADD231PH
VFNMADD231SH
VFNMSUB132BF16
VFNMSUB132PH
VFNMSUB132SH
VFNMSUB213BF16
VFNMSUB213PH
VFNMSUB213SH
VFNMSUB231BF16
VFNMSUB231PH
VFNMSUB231SH
VFPCLASSBF16
VFPCLASSPH
VFPCLASSSH
VGETEXPBF16
VGETEXPPH
VGETEXPSH
VGETMANTBF16
VGETMANTPH
VGETMANTSH
VMAXBF16
VMAXPH
VMAXSH
VMINBF16
VMINMAXBF16
VMINMAXPD
VMINMAXPH
VMINMAXPS
VMINMAXSD
VMINMAXSH
VMINMAXSS
VMINPH
VMINSH
VMOVSH
VMULBF16
VMULPH
VMULSH
VP2INTERSECTD
VP2INTERSECTQ
VPCOMPRESSB
VPCOMPRESSW
VPDPBSSD
VPDPBSSDS
VPDPBSUD
VPDPBSUDS
VPDPBUUD
VPDPBUUDS
VPDPWSUD
VPDPWSUDS
VPDPWUSD
VPDPWUSDS
VPDPWUUD
VPDPWUUDS
VPEXPANDB
VPEXPANDW
VPSHLDVD
VPSHLDVQ
VPSHLDVW
VPSHRDVD
VPSHRDVQ
VPSHRDVW
VPSHUFBITQMB
VRCPBF16
VRCPPH
VRCPSH
VREDUCE16
VREDUCEPH
VREDUCESH
VRNDSCALEBF16
VRNDSCALEPH
VRNDSCALESH
VRSQRTBF16
VRSQRTPH
VRSQRTSH
VSCALEFBF16
VSCALEFPH
VSCALEFSH
VSHA512MSG1
VSHA512MSG2
VSHA512RNDS2
VSM3MSG1
VSM3MSG2
VSM3RNDS2
VSM4KEY4
VSM4RNDS4
VSQRTBF16
VSQRTPH
VSQRTSH
VSUBBF16
VSUBPH
VSUBSH
VUCOMISH
VUCOMXSD
VUCOMXSH
VUCOMXSS

↑ IihHandlers: assemble AVX10.2 machine instructions which compute using mostly floating-point numbers with half and byte precision (FP16, E4M3, E5M2).
See also: IiHandlers

iih PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
    INCLUDEHEAD euroasm.htm, \  Interface (structures, symbols and macros) of other modules used in this source.
                ea.htm,eaopt.htm,exp.htm,ii.htm,msg.htm,pgm.htm,pgmopt.htm,sss.htm,stm.htm,sym.htm

iih HEAD ; Start of module interface.

↑ %IihList: enumerates machine instructions of this family which €ASM can assemble.
Each instruction declared in %IihList requires the corresponding handler in this file.
See also: DictLookupIi

%IihList %SET   \
VADDBF16,       \
VADDPH,         \
VADDSH,         \
VBCSTNEBF162PS, \
VBCSTNESH2PS,   \
VCMPBF16,       \
VCMPPH,         \
VCMPSH,         \
VCOMISBF16,     \
VCOMISH,        \
VCOMXSD,        \
VCOMXSH,        \
VCOMXSS,        \
VCVT2PH2BF8,    \
VCVT2PH2BF8S,   \
VCVT2PH2HF8,    \
VCVT2PH2HF8S,   \
VCVT2PS2PHX,    \
VCVTBF162IBS,   \
VCVTBF162IUBS,  \
VCVTBIASPH2BF8, \
VCVTBIASPH2BF8S,\
VCVTBIASPH2HF8, \
VCVTBIASPH2HF8S,\
VCVTDQ2PH,      \
VCVTHF82PH,     \
VCVTNE2PS2BF16, \
VCVTNEEBF162PS, \
VCVTNEEPH2PS,   \
VCVTNEOBF162PS, \
VCVTNEOPH2PS,   \
VCVTNEPS2BF16,  \
VCVTPD2PH,      \
VCVTPH2BF8,     \
VCVTPH2BF8S,    \
VCVTPH2DQ,      \
VCVTPH2HF8,     \
VCVTPH2HF8S,    \
VCVTPH2IBS,     \
VCVTPH2IUBS,    \
VCVTPH2PD,      \
VCVTPH2PSX,     \
VCVTPH2QQ,      \
VCVTPH2UDQ,     \
VCVTPH2UQQ,     \
VCVTPH2UW,      \
VCVTPH2W,       \
VCVTPS2IBS,     \
VCVTPS2IUBS,    \
VCVTPS2PHX,     \
VCVTQQ2PH,      \
VCVTSD2SH,      \
VCVTSH2SD,      \
VCVTSH2SI,      \
VCVTSH2SS,      \
VCVTSH2USI,     \
VCVTSI2SH,      \
VCVTSS2SH,      \
VCVTSS2USI,     \
VCVTTBF162IBS,  \
VCVTTBF162IUBS, \
VCVTTPD2DQS,    \
VCVTTPD2QQS,    \
VCVTTPD2UDQS,   \
VCVTTPD2UQQS,   \
VCVTTPH2DQ,     \
VCVTTPH2IBS,    \
VCVTTPH2IUBS,   \
VCVTTPH2QQ,     \
VCVTTPH2UDQ,    \
VCVTTPH2UQQ,    \
VCVTTPH2UW,     \
VCVTTPH2W,      \
VCVTTPS2DQS,    \
VCVTTPS2IBS,    \
VCVTTPS2IUBS,   \
VCVTTPS2QQS,    \
VCVTTPS2UDQS,   \
VCVTTPS2UQQS,   \
VCVTTSD2SIS,    \
VCVTTSD2USIS,   \
VCVTTSH2SI,     \
VCVTTSH2USI,    \
VCVTTSS2SIS,    \
VCVTTSS2USIS,   \
VCVTUDQ2PH,     \
VCVTUQQ2PH,     \
VCVTUSI2SH,     \
VCVTUW2PH,      \
VCVTW2PH,       \
VDIVBF16,       \
VDIVPH,         \
VDIVSH,         \
VDPBF16PS,      \
VDPPHPS,        \
VFCMADDCPH,     \
VFCMADDCSH,     \
VFCMULCPH,      \
VFCMULCSH,      \
VFMADD132BF16,  \
VFMADD132PH,    \
VFMADD132SH,    \
VFMADD213BF16,  \
VFMADD213PH,    \
VFMADD213SH,    \
VFMADD231BF16,  \
VFMADD231PH,    \
VFMADD231SH,    \
VFMADDCPH,      \
VFMADDCSH,      \
VFMADDSUB132PS, \
VFMADDSUB213PS, \
VFMADDSUB231PS, \
VFMSUB132BF16,  \
VFMSUB132PH,    \
VFMSUB132SH,    \
VFMSUB213BF16,  \
VFMSUB213PH,    \
VFMSUB213SH,    \
VFMSUB231BF16,  \
VFMSUB231PH,    \
VFMSUB231SH,    \
VFMSUBADD132PS, \
VFMSUBADD213PS, \
VFMSUBADD231PS, \
VFMULCPH,       \
VFMULCSH,       \
VFNMADD132BF16, \
VFNMADD132PH,   \
VFNMADD132SH,   \
VFNMADD213BF16, \
VFNMADD213PH,   \
VFNMADD213SH,   \
VFNMADD231BF16, \
VFNMADD231PH,   \
VFNMADD231SH,   \
VFNMSUB132BF16, \
VFNMSUB132PH,   \
VFNMSUB132SH,   \
VFNMSUB213BF16, \
VFNMSUB213PH,   \
VFNMSUB213SH,   \
VFNMSUB231BF16, \
VFNMSUB231PH,   \
VFNMSUB231SH,   \
VFPCLASSBF16,   \
VFPCLASSPH,     \
VFPCLASSSH,     \
VGETEXPBF16,    \
VGETEXPPH,      \
VGETEXPSH,      \
VGETMANTBF16,   \
VGETMANTPH,     \
VGETMANTSH,     \
VMAXBF16,       \
VMAXPH,         \
VMAXSH,         \
VMINBF16,       \
VMINMAXBF16,    \
VMINMAXPD,      \
VMINMAXPH,      \
VMINMAXPS,      \
VMINMAXSD,      \
VMINMAXSH,      \
VMINMAXSS,      \
VMINPH,         \
VMINSH,         \
VMOVSH,         \
VMULBF16,       \
VMULPH,         \
VMULSH,         \
VP2INTERSECTD,  \
VP2INTERSECTQ,  \
VPCOMPRESSB,    \
VPCOMPRESSW,    \
VPDPBSSD,       \
VPDPBSSDS,      \
VPDPBSUD,       \
VPDPBSUDS,      \
VPDPBUUD,       \
VPDPBUUDS,      \
VPDPWSUD,       \
VPDPWSUDS,      \
VPDPWUSD,       \
VPDPWUSDS,      \
VPDPWUUD,       \
VPDPWUUDS,      \
VPEXPANDB,      \
VPEXPANDW,      \
VPSHLDVD,       \
VPSHLDVQ,       \
VPSHLDVW,       \
VPSHRDVD,       \
VPSHRDVQ,       \
VPSHRDVW,       \
VPSHUFBITQMB,   \
VRCPBF16,       \
VRCPPH,         \
VRCPSH,         \
VREDUCEBF16,    \
VREDUCEPH,      \
VREDUCESH,      \
VRNDSCALEBF16,  \
VRNDSCALEPH,    \
VRNDSCALESH,    \
VRSQRTBF16,     \
VRSQRTPH,       \
VRSQRTSH,       \
VSCALEFBF16,    \
VSCALEFPH,      \
VSCALEFSH,      \
VSHA512MSG1,    \
VSHA512MSG2,    \
VSHA512RNDS2,   \
VSM3MSG1,       \
VSM3MSG2,       \
VSM3RNDS2,      \
VSM4KEY4,       \
VSM4RNDS4,      \
VSQRTBF16,      \
VSQRTPH,        \
VSQRTSH,        \
VSUBBF16,       \
VSUBPH,         \
VSUBSH,         \
VUCOMISH,       \
VUCOMXSD,       \
VUCOMXSH,       \
VUCOMXSS,       \

;

 ENDHEAD iih ; End of module interface.

↑ VADDBF16: Add packed BF16 values.
Reference: EVEX.512.66.MAP5.W0 58 /r VADDBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5211

IihVADDBF16:: PROC
  IiRequire AVX10
  IiAllowBroadcasting WORD
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiEmitOpcode 0x58
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVADDBF16::

↑ VCMPBF16: Compare packed BF16 values.
Reference: EVEX.512.F2.0F3A.W0 C2 /r /ib VCMPBF16 k1{k2}, zmm2, zmm3/m512/m16bcst, imm8 FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r
Documentation: [IntelAVX10.2]
Tested by: t5261

IihVCMPBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,IMM
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xC2
  IiDisp8EVEX FULL2
  IiEmitImm Operand4, BYTE, Max=31
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat krg.xmm.xmm.imm, krg.xmm.mem.imm, krg.ymm.ymm.imm, krg.ymm.mem.imm, \
                   krg.zmm.zmm.imm, krg.zmm.mem.imm
.krg.xmm.mem.imm:
.krg.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.krg.ymm.mem.imm:
.krg.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.krg.zmm.zmm.imm:
.krg.zmm.mem.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
 ENDP IihVCMPBF16::

↑ VCOMISBF16: Compare BF16 values to ZF,PF,CF.
Reference: EVEX.LLIG.66.MAP5.W0 2F /r VCOMISBF16 xmm1, xmm2/m16 SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5261

IihVCOMISBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEncoding DATA=WORD
  IiEmitOpcode 0x2F
  IiDisp8EVEX SCALAR2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP5.W0
  RET
 ENDP IihVCOMISBF16::

↑ VCOMXSD: Compare FP64 values to OF,SF,ZF,PF,CF.
Reference: EVEX.LLIG.F2.0F.W1 2F /r VCOMXSD xmm1, xmm2/m64{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5261

IihVCOMXSD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiEncoding DATA=QWORD
  IiAllowSuppressing Register=xmm
  IiEmitOpcode 0x2F
  IiDisp8EVEX SCALAR8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F2.0F.W1
  RET
 ENDP IihVCOMXSD::

↑ VCOMXSH: Compare FP16 values to OF,SF,ZF,PF,CF.
Reference: EVEX.LLIG.F3.MAP5.W0 2F /r VCOMXSH xmm1, xmm2/m16{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5261

IihVCOMXSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiEncoding DATA=WORD
  IiAllowSuppressing Register=xmm
  IiEmitOpcode 0x2F
  IiDisp8EVEX SCALAR2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVCOMXSH::

↑ VCOMXSS: Compare FP32 values to OF,SF,ZF,PF,CF.
Reference: EVEX.LLIG.F3.0F.W0 2F /r VCOMXSS xmm1, xmm2/m32{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5261

IihVCOMXSS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiEncoding DATA=DWORD
  IiAllowSuppressing Register=xmm
  IiEmitOpcode 0x2F
  IiDisp8EVEX SCALAR4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.0F.W0
  RET
 ENDP IihVCOMXSS::

↑ VCVT2PH2BF8: Convert 16|32|64 packed FP16 to 16|32|64 packed BF8 E5M2.
Reference: EVEX.128.F2.0F38.W0 74 /r VCVT2PH2BF8 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVT2PH2BF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W0
  RET
 ENDP IihVCVT2PH2BF8::

↑ VCVT2PH2BF8S: Convert 16|32|64 packed FP16 to 16|32|64 packed saturated BF8 E5M2.
Reference: EVEX.128.F2.MAP5.W0 74 /r VCVT2PH2BF8S zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVT2PH2BF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVT2PH2BF8S::

↑ VCVT2PH2HF8: Convert 16|32|64 packed FP16 to 16|32|64 packed HF8 E4M3.
Reference: EVEX.512.F2.MAP5.W0 18 /r VCVT2PH2HF8 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVT2PH2HF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x18
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVT2PH2HF8::

↑ VCVT2PH2HF8S: Convert 16|32|64 packed FP16 to 16|32|64 packed HF8 E4M3.
Reference: EVEX.512.F2.MAP5.W0 1B /r VCVT2PH2HF8S zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVT2PH2HF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x1B
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVT2PH2HF8S::

↑ VCVT2PS2PHX: Convert 16|32|64 packed FP16 to 16|32|64 packed HF8 E4M3.
Reference: EVEX.512.66.0F38.W0 67 /r VCVT2PS2PHX zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst{er} FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5234

IihVCVT2PS2PHX:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING,SAE
  IiAllowBroadcasting DWORD
  IiEmitOpcode 0x67
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVCVT2PS2PHX::

↑ VCVTPH2BF8: Convert 8|16|32 packed FP16 to 8|16|32 packed BF8 E5M2.
Reference: EVEX.512.F3.0F38.W0 74 /r VCVT2PH2BF8 ymm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVTPH2BF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEncoding DATA=OWORD
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.xmm.ymm:
  IiEncoding DATA=YWORD
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEncoding DATA=ZWORD
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVCVTPH2BF8::

↑ VCVTPH2BF8S: Convert 8|16|32 packed FP16 to 8|16|32 packed saturated BF8 E5M2.
Reference: EVEX.512.F3.MAP5.W0 74 /r VCVTPH2BF8S ymm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVTPH2BF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEncoding DATA=OWORD
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
.xmm.ymm:
  IiEncoding DATA=YWORD
  IiEmitPrefix EVEX.256.F3.MAP5.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEncoding DATA=ZWORD
  IiEmitPrefix EVEX.512.F3.MAP5.W0
  RET
 ENDP IihVCVTPH2BF8S::

↑ VCVTPH2HF8: Convert 8|16|32 packed FP16 to 8|16|32 packed HF8 E4M3.
Reference: EVEX.512.F3.MAP5.W0 18 /r VCVTPH2HF8 ymm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVTPH2HF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x18
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm, YWORD=.xmm.ymm
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEncoding DATA=OWORD
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
.xmm.ymm:
  IiEncoding DATA=YWORD
  IiEmitPrefix EVEX.256.F3.MAP5.W0
  RET
.ymm.mem:
.ymm.zmm:
  IiEncoding DATA=ZWORD
  IiEmitPrefix EVEX.512.F3.MAP5.W0
  RET
 ENDP IihVCVTPH2HF8::

↑ VCVTPH2HF8S: Convert 8|16|32 packed FP16 to 8|16|32 packed saturated HF8 E4M3.
Reference: EVEX.512.F3.MAP5.W0 18 /r VCVT2PH2HF8 ymm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5232

IihVCVTPH2HF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x1B
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm, YWORD=.xmm.ymm
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEncoding DATA=OWORD
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
.xmm.ymm:
  IiEncoding DATA=YWORD
  IiEmitPrefix EVEX.256.F3.MAP5.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEncoding DATA=ZWORD
  IiEmitPrefix EVEX.512.F3.MAP5.W0
  RET
 ENDP IihVCVTPH2HF8S::

↑ VDIVBF16: Divide BF16 values.
Reference: EVEX.512.66.MAP5.W0 5E /r VDIVBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst SCALAR FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5211

IihVDIVBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x5E
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVDIVBF16::

↑ VFMADD132BF16: Packed multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 98 /r VFMADD132BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMADD132BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x98
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMADD132BF16::

↑ VFMADD213BF16: Packed multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 A8 /r VFMADD213BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMADD213BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xA8
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMADD213BF16::

↑ VFMADD231BF16: Packed multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 B8 /r VFMADD231BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst SCALAR FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMADD231BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xB8
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMADD231BF16::

↑ VFMSUB132BF16: Packed multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 9A /r VFMSUB132BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMSUB132BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x9A
  IiDisp8EVEX FULL
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMSUB132BF16::

↑ VFMSUB213BF16: Packed multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 AA /r VFMSUB213BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMSUB213BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xAA
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMSUB213BF16::

↑ VFMSUB231BF16: Packed multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 BA /r VFMSUB231BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFMSUB231BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xBA
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFMSUB231BF16::

↑ VFNMADD132BF16: Packes negated multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 9C /r VFNMADD132BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMADD132BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x9C
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMADD132BF16::

↑ VFNMADD213BF16: Packes negated multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 AC /r VFNMADD213BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMADD213BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xAC
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMADD213BF16::

↑ VFNMADD231BF16: Packes negated multiply-add BF16 values.
Reference: EVEX.512.NP.MAP6.W0 BC /r VFNMADD231BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMADD231BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xBC
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMADD231BF16::

↑ VFNMSUB132BF16: Packes negated multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 9E /r VFNMSUB132BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMSUB132BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x9E
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMSUB132BF16::

↑ VFNMSUB213BF16: Packes negated multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 AE /r VFNMSUB213BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMSUB213BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xAE
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMSUB213BF16::

↑ VFNMSUB231BF16: Packes negated multiply-subtract BF16 values.
Reference: EVEX.128.NP.MAP6.W0 BE /r VFNMSUB231BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t4651

IihVFNMSUB231BF16:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0xBE
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVFNMSUB231BF16::

↑ VCVTBF162IBS: Convert BF16 to saturated signed 8-bit integer.
Reference: EVEX.512.F2.MAP5.W0 69 /r VCVTBF162IBS xmm1{k1}{z}, xmm2/m128/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5236

IihVCVTBF162IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x69
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTBF162IBS::

↑ VCVTBF162IUBS: Convert BF16 to saturated unsigned 8-bit integer.
Reference: EVEX.512.F2.MAP5.W0 6B /r VCVTBF162IUBS zmm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5236

IihVCVTBF162IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x6B
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTBF162IUBS::

↑ VCVTTBF162IBS: Convert BF16 to saturated truncated signed 8-bit integer.
Reference: EVEX.512.F2.MAP5.W0 68 /r VCVTTBF162IBS xmm1{k1}{z}, xmm2/m128/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5236

IihVCVTTBF162IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x68
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTTBF162IBS::

↑ VCVTTBF162IUBS: Convert BF16 to saturated truncated unsigned 8-bit integer.
Reference: EVEX.512.F2.MAP5.W0 6A /r VCVTTBF162IUBS zmm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5236

IihVCVTTBF162IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x6A
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTTBF162IUBS::

↑ VCVTBIASPH2BF8: Convert bias rounded addition to FP8 E5M2.
Reference: EVEX.512.NP.0F38.W0 74 /r VCVTBIASPH2BF8 ymm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5237

IihVCVTBIASPH2BF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, xmm.ymm.ymm, xmm.ymm.mem, ymm.zmm.zmm, ymm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.xmm.ymm.ymm:
.xmm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.ymm.zmm.zmm:
.ymm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVCVTBIASPH2BF8::

↑ VCVTBIASPH2BF8S: Convert bias rounded truncated addition to FP8 E5M2.
Reference: EVEX.512.NP.MAP5.W0 74 /r VCVTBIASPH2BF8S ymm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5237

IihVCVTBIASPH2BF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x74
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, xmm.ymm.ymm, xmm.ymm.mem, ymm.zmm.zmm, ymm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.xmm.ymm.ymm:
.xmm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.ymm.zmm.zmm:
.ymm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTBIASPH2BF8S::

↑ VCVTBIASPH2HF8: Convert bias rounded addition to FP8 E4M3.
Reference: EVEX.512.NP.MAP5.W0 18 /r VCVTBIASPH2HF8 ymm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5237

IihVCVTBIASPH2HF8:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x18
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, xmm.ymm.ymm, xmm.ymm.mem, ymm.zmm.zmm, ymm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.xmm.ymm.ymm:
.xmm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.ymm.zmm.zmm:
.ymm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTBIASPH2HF8::

↑ VCVTBIASPH2HF8S: Convert bias rounded truncated addition to FP8 E4M3.
Reference: EVEX.512.NP.MAP5.W0 1B /r VCVTBIASPH2HF8S ymm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5237

IihVCVTBIASPH2HF8S:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x1B
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, xmm.ymm.ymm, xmm.ymm.mem, ymm.zmm.zmm, ymm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.xmm.ymm.ymm:
.xmm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.ymm.zmm.zmm:
.ymm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTBIASPH2HF8S::

↑ VCVTHF82PH: Convert FP8 E4M3 to FP16.
Reference: EVEX.512.F2.MAP5.W0 1E /r VCVTHF82PH zmm1{k1}{z}, ymm2/m256 HALF MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5236

IihVCVTHF82PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiEmitOpcode 0x1E
  IiDisp8EVEX HALF2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTHF82PH::

↑ VCVTPH2IBS: Convert FP16 to rounded signed 8-bit integer.
Reference: EVEX.512.NP.MAP5.W0 69 /r VCVTPH2IBS zmm1{k1}{z}, zmm2/m512/m16bcst {er} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTPH2IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting WORD
  IiAllowRounding
  IiEmitOpcode 0x69
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTPH2IBS::

↑ VCVTPH2IUBS: Convert FP16 to rounded unsigned 8-bit integer.
Reference: EVEX.512.NP.MAP5.W0 6B /r VCVTPH2IUBS zmm1{k1}{z}, zmm2/m512/m16bcst {er} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTPH2IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting WORD
  IiAllowRounding
  IiEmitOpcode 0x6B
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTPH2IUBS::

↑ VCVTTPH2IBS: Convert FP16 to truncated signed 8-bit integer.
Reference: EVEX.512.NP.MAP5.W0 68 /r VCVTTPH2IBS zmm1{k1}{z}, zmm2/m512/m16bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTTPH2IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x68
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTTPH2IBS::

↑ VCVTTPH2IUBS: Convert FP16 to truncated unsigned 8-bit integer.
Reference: EVEX.512.NP.MAP5.W0 6A /r VCVTTPH2IUBS zmm1{k1}{z}, zmm2/m512/m16bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTTPH2IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting WORD
  IiAllowSuppressing
  IiEmitOpcode 0x6A
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTTPH2IUBS::

↑ VCVTPS2IBS: Convert 4|8|16 FP32 to saturated signed 8-bit integer.
Reference: EVEX.128.66.MAP5.W0 69 /r VCVTPS2IBS zmm1{k1}{z}, zmm2/m512/m32bcst {er} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTPS2IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting DWORD
  IiAllowRounding
  IiEmitOpcode 0x69
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPS2IBS::

↑ VCVTPS2IUBS: Convert FP32 to saturated unsigned 8-bit integer.
Reference: EVEX.512.66.MAP5.W0 6B /r VCVTPS2IUBS zmm1{k1}{z}, zmm2/m512/m32bcst {er} FULL FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTPS2IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting DWORD
  IiAllowRounding
  IiEmitOpcode 0x6B
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPS2IUBS::

↑ VCVTTPS2IBS: Convert FP32 to truncated saturated signed 8-bit integer.
Reference: EVEX.512.66.MAP5.W0 68 /r VCVTTPS2IBS zmm1{k1}{z}, zmm2/m512/m32bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTTPS2IBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiEmitOpcode 0x68
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTTPS2IBS::

↑ VCVTTPS2IUBS: Convert FP32 to truncated saturated unsigned 8-bit integer.
Reference: EVEX.512.66.MAP5.W0 6A /r VCVTTPS2IUBS zmm1{k1}{z}, zmm2/m512/m32bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5238

IihVCVTTPS2IUBS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiEmitOpcode 0x6A
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTTPS2IUBS::

↑ VCVTTPD2DQS: Convert packed FP64 to packed truncated saturated 32bit integer.
Reference: EVEX.512.NP.MAP5.W1 6D /r VCVTTPD2DQS xmm1{k1}{z}, xmm2/m128/m64bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPD2DQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting QWORD
  IiAllowRounding
  IiEmitOpcode 0x6D
  IiDisp8EVEX FULL8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.mem, ymm.zmm
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W1
  RET
.xmm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W1
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W1
  RET
 ENDP IihVCVTTPD2DQS::

↑ VCVTTPD2QQS: Convert packed FP64 to packed truncated saturated 64bit integer.
Reference: EVEX.512.66.MAP5.W1 6D /r VCVTTPD2QQS zmm1{k1}{z}, zmm2/m512/m64bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPD2QQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting QWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiAllowRounding
  IiEmitOpcode 0x6D
  IiDisp8EVEX FULL8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W1
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W1
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W1
  RET
 ENDP IihVCVTTPD2QQS::

↑ VCVTTPD2UDQS: Convert packed FP64 to packed truncated saturated unsigned 32bit integer.
Reference: EVEX.512.NP.MAP5.W1 6C /r VCVTTPD2UDQS ymm1{k1}{z}, zmm2/m512/m64bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPD2UDQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting QWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiAllowRounding
  IiEmitOpcode 0x6C
  IiDisp8EVEX FULL8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.mem, ymm.zmm
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W1
  RET
.xmm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W1
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W1
  RET
 ENDP IihVCVTTPD2UDQS::

↑ VCVTTPD2UQQS: Convert packed FP64 to packed truncated saturated unsigned 64bit integer.
Reference: EVEX.512.66.MAP5.W1 6C /r VCVTTPD2UQQS zmm1{k1}{z}, zmm2/m512/m64bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPD2UQQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting QWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiAllowRounding
  IiEmitOpcode 0x6C
  IiDisp8EVEX FULL8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W1
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W1
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W1
  RET
 ENDP IihVCVTTPD2UQQS::

↑ VCVTTPS2DQS: Convert packed FP32 to packed truncated saturated 32bit integer.
Reference: EVEX.512.NP.MAP5.W0 6D /r VCVTTPS2DQS zmm1{k1}{z}, zmm2/m512/m32bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPS2DQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowRounding
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiEmitOpcode 0x6D
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTTPS2DQS::

↑ VCVTTPS2QQS: Convert packed FP32 to packed truncated saturated 64bit integer.
Reference: EVEX.512.66.MAP5.W0 6D /r VCVTTPS2QQS zmm1{k1}{z}, ymm2/m256/m32bcst {sae} HALF MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPS2QQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiAllowRounding
  IiEmitOpcode 0x6D
  IiDisp8EVEX HALF4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTTPS2QQS::

↑ VCVTTPS2UDQS: Convert packed FP32 to packed truncated saturated unsigned 32bit integer.
Reference: EVEX.512.NP.MAP5.W0 6C /r VCVTTPS2UDQS zmm1{k1}{z}, zmm2/m512/m32bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPS2UDQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiEmitOpcode 0x6C
  IiDisp8EVEX FULL4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTTPS2UDQS::

↑ VCVTTPS2UQQS: Convert packed FP32 to packed truncated saturated unsigned 64bit integer.
Reference: EVEX.512.66.MAP5.W0 6C /r VCVTTPS2UQQS zmm1{k1}{z}, ymm2/m256/m32bcst {sae} FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5239

IihVCVTTPS2UQQS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting DWORD
  IiAllowSuppressing Operand=DL, Register=zmm, Swizzle=no
  IiEmitOpcode 0x6C
  IiDisp8EVEX HALF4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTTPS2UQQS::

↑ VCVTTSD2SIS: Convert FP64 to a truncated saturated 32-bit or 64-bit integer.
Reference: EVEX.LLIG.F2.MAP5.W0 6D /r VCVTTSD2SIS r32, xmm1/m64 {sae} EVEX.LLIG.F2.MAP5.W1 6D /r VCVTTSD2SIS r64, xmm1/m64 {sae} SCALAR MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5234

IihVCVTTSD2SIS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Register=xmm, Swizzle=no
  IiEmitOpcode 0x6D
  IiDisp8EVEX SCALAR8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEncoding DATA=DWORD
  IiEmitPrefix EVEX.LLIG.F2.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEncoding DATA=QWORD
  IiEmitPrefix EVEX.LLIG.F2.MAP5.W1
  RET
 ENDP IihVCVTTSD2SIS::

↑ VCVTTSD2USIS: Convert FP64 to a truncated saturated unsigned 32-bit or 64-bit integer.
Reference: EVEX.LLIG.F2.MAP5.W0 6C /r VCVTTSD2USIS r32, xmm1/m64 {sae} EVEX.LLIG.F2.MAP5.W1 6C /r VCVTTSD2USIS r64, xmm1/m64 {sae} SCALAR MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5234

IihVCVTTSD2USIS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Register=xmm, Swizzle=no
  IiEmitOpcode 0x6C
  IiDisp8EVEX SCALAR8
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEmitPrefix EVEX.LLIG.F2.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEmitPrefix EVEX.LLIG.F2.MAP5.W1
  RET
 ENDP IihVCVTTSD2USIS::

↑ VCVTTSS2SIS: Convert FP32 to a truncated saturated 32-bit or 64-bit integer.
Reference: EVEX.LLIG.F3.MAP5.W0 6D /r VCVTTSS2SIS r32, xmm1/m64 {sae} EVEX.LLIG.F3.MAP5.W1 6D /r VCVTTSS2SIS r64, xmm1/m64 {sae} SCALAR MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5234

IihVCVTTSS2SIS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Register=xmm, Swizzle=no
  IiEmitOpcode 0x6D
  IiDisp8EVEX SCALAR4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTTSS2SIS::

↑ VCVTTSS2USIS: Convert FP32 to a truncated saturated unsigned 32-bit or 64-bit integer.
Reference: EVEX.LLIG.F3.MAP5.W0 6C /r VCVTTSS2USIS r32, xmm1/m64 {sae} EVEX.LLIG.F3.MAP5.W1 6C /r VCVTTSS2USIS r64, xmm1/m64 {sae} SCALAR MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5234

IihVCVTTSS2USIS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Register=xmm, Swizzle=no
  IiEmitOpcode 0x6C
  IiDisp8EVEX SCALAR4
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTTSS2USIS::

↑ VDPPHPS: Perform dot-product of two FP16 pairs and accumulate into a packed FP32.
Reference: EVEX.512.NP.0F38.W0 52 /r VDPPHPS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(rw) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5280

IihVDPPHPS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting DWORD
  IiEmitOpcode 0x52
  IiDisp8EVEX FULL4
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm,xmm.xmm.mem,ymm.ymm.ymm,ymm.ymm.mem,zmm.zmm.zmm,zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVDPPHPS::

↑ VFPCLASSBF16: Classify packed BF16.
Reference: EVEX.512.F2.0F3A.W0 66 /r /ib VFPCLASSBF16 k1{k2}, zmm2/m512/m16bcst, imm8 FULL MODRM.REG(w) MODRM.R/M(r) IMM8(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5430

IihVFPCLASSBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,BCST
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x66
  IiEmitImm Operand3, BYTE, Max=255
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat krg.xmm.imm, krg.ymm.imm, krg.zmm.imm, krg.mem.imm
.krg.mem.imm:
  IiDispatchData OWORD=.krg.xmm.imm:, YWORD=.krg.ymm.imm:, ZWORD=.krg.zmm.imm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.krg.xmm.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.krg.ymm.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.krg.zmm.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
  RET
 ENDP IihVFPCLASSBF16::

↑ VGETEXPBF16: Extract biased exponents to BF16.
Reference: EVEX.512.NP.MAP6.W0 42 /r VGETEXPBF16 zmm1{k1}{z}, zmm2/m512/m16bcs FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5460

IihVGETEXPBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x42
  IiDisp8EVEX FULL2
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVGETEXPBF16::

↑ VGETMANTBF16: Convert BF16 to BF16 with the mantissa normalization by imm8.
Reference: EVEX.512.F2.0F3A.W0 26 /r /ib VGETMANTBF16 zmm1{k1}{z}, zmm2/m512/m16bcst, imm8 FULL MODRM.REG(w) MODRM.R/M(r) IMM8(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5462

IihVGETMANTBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x26
  IiDisp8EVEX FULL2
  IiEmitImm Operand3, BYTE, Max=255
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.ymm.ymm.imm:
.ymm.mem.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
 ENDP IihVGETMANTBF16::

↑ VMAXBF16: Return maximum value of two FP16.
Reference: EVEX.512.66.MAP5.W0 5F /r VMAXBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5215

IihVMAXBF16:: PROC
  IiRequire AVX10
  IiAllowBroadcasting WORD
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiEmitOpcode 0x5F
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVMAXBF16::

↑ VMINBF16: Return minimum value of two FP16.
Reference: EVEX.512.66.MAP5.W0 5D /r VMINBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5215

IihVMINBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x5D
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVMINBF16::

↑ VMINMAXBF16: Perform min/max comparison between two SIMD registers.
Reference: EVEX.512.F2.0F3A.W0 52 /r /ib VMINMAXBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst, imm8 FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiEmitOpcode 0x52
  IiDisp8EVEX FULL2
  IiEmitImm Operand4, BYTE, Max=255
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, \
                   zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
 ENDP IihVMINMAXBF16::

↑ VMINMAXPD: Perform min/max comparison between two SIMD registers.
Reference: EVEX.512.66.0F3A.W1 52 /r /ib VMINMAXPD zmm1{k1}{z}, zmm2, zmm3/m512/m64bcst {sae}, imm8 FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXPD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING,SAE
  IiAllowBroadcasting QWORD
  IiAllowSuppressing Operand=DH, Register=zmm, Swizzle=no
  IiEmitOpcode 0x52
  IiDisp8EVEX FULL8
  IiEmitImm Operand4, BYTE, Max=0x1F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, \
                   zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.66.0F3A.W1
  RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.66.0F3A.W1
  RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
  IiEmitPrefix EVEX.512.66.0F3A.W1
  RET
 ENDP IihVMINMAXPD::

↑ VMINMAXPH: Perform min/max comparison between two SIMD registers.
Reference: EVEX.512.NP.0F3A.W0 52 /r /ib VMINMAXPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {sae}, imm8 FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXPH:: PROC
  IiRequire AVX10
  IiAllowBroadcasting WORD
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=zmm, Swizzle=no
  IiEmitOpcode 0x52
  IiDisp8EVEX FULL2
  IiEmitImm Operand4, BYTE, Max=0x1F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, \
                   zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVMINMAXPH::

↑ VMINMAXPS: Perform min/max comparison between two SIMD registers.
Reference: EVEX.512.66.0F3A.W0 52 /r /ib VMINMAXPS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {sae}, imm8 FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXPS:: PROC
  IiRequire AVX10
  IiAllowBroadcasting DWORD
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=zmm, Swizzle=no
  IiEmitOpcode 0x52
  IiDisp8EVEX FULL4
  IiEmitImm Operand4, BYTE, Max=255
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm, ymm.ymm.ymm.imm, ymm.ymm.mem.imm, \
                   zmm.zmm.zmm.imm, zmm.zmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.66.0F3A.W0
  RET
.ymm.ymm.mem.imm:
.ymm.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.66.0F3A.W0
  RET
.zmm.zmm.zmm.imm:
.zmm.zmm.mem.imm:
  IiEmitPrefix EVEX.512.66.0F3A.W0
  RET
 ENDP IihVMINMAXPS::

↑ VMINMAXSD: Perform min/max comparison between two elements.
Reference: EVEX.LLIG.66.0F3A.W1 53 /r /ib VMINMAXSD xmm1{k1}{z}, xmm2, xmm3/m64 {sae}, imm8 SCALAR MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXSD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=xmm, Swizzle=no
  IiEmitOpcode 0x53
  IiDisp8EVEX SCALAR8
  IiEmitImm Operand4, BYTE
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.66.0F3A.W1
  RET
 ENDP IihVMINMAXSD::

↑ VMINMAXSH: Perform min/max comparison between two elements.
Reference: EVEX.512.NP.0F3A.W0 53 /r /ib VMINMAXSH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {sae}, imm8 SCALAR MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=xmm, Swizzle=no
  IiEmitOpcode 0x53
  IiDisp8EVEX SCALAR2
  IiEmitImm Operand4, BYTE, Max=0x1F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
 ENDP IihVMINMAXSH::

↑ VMINMAXSS: Perform min/max comparison between two elements.
Reference: EVEX.512.66.0F3A.W0 53 /r /ib VMINMAXSS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {sae}, imm8 SCALAR MODRM.REG(w) VVVV(r) MODRM.R/M(r) IMM8(r)
Documentation: [IntelAVX10.2]
Tested by: t5218

IihVMINMAXSS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=xmm, Swizzle=no
  IiEmitOpcode 0x53
  IiDisp8EVEX SCALAR4
  IiEmitImm Operand4, BYTE, Max=0x1F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.66.0F3A.W0
  RET
 ENDP IihVMINMAXSS::

↑ VMULBF16: Multiply packed BF16 values.
Reference: EVEX.512.66.MAP5.W0 59 /r VMULBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5211

IihVMULBF16:: PROC
  IiRequire AVX10
  IiAllowBroadcasting WORD
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiEmitOpcode 0x59
  IiDisp8EVEX FULL2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVMULBF16::

↑ VPDPBSSD: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.F2.0F38.W0 50 /r VPDPBSSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBSSD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x50
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F2.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W0
  RET
 ENDP IihVPDPBSSD::

↑ VPDPBSSDS: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.F2.0F38.W0 51 /r VPDPBSSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBSSDS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x51
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F2.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W0
  RET
 ENDP IihVPDPBSSDS::

↑ VPDPBSUD: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.F3.0F38.W0 50 /r VPDPBSUD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBSUD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x50
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVPDPBSUD::

↑ VPDPBSUDS: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.F3.0F38.W0 51 /r VPDPBSUDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBSUDS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x51
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVPDPBSUDS::

↑ VPDPBUUD: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.NP.0F38.W0 50 /r VPDPBUUD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBUUD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x50
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVPDPBUUD::

↑ VPDPBUUDS: Multiply BYTEs and accumulate results to DWORD.
Reference: EVEX.512.NP.0F38.W0 51 /r VPDPBUUDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5912

IihVPDPBUUDS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x51
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVPDPBUUDS::

↑ VPDPWSUD: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.F3.0F38.W0 D2 /r VPDPWSUD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWSUD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVPDPWSUD::

↑ VPDPWSUDS: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.F3.0F38.W0 D3 /r VPDPWSUDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWSUDS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD3
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVPDPWSUDS::

↑ VPDPWUSD: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.66.0F38.W0 D2 /r VPDPWUSD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWUSD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPDPWUSD::

↑ VPDPWUSDS: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.66.0F38.W0 D3 /r VPDPWUSDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWUSDS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD3
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPDPWUSDS::

↑ VPDPWUUD: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.NP.0F38.W0 D2 /r VPDPWUUD zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWUUD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD2
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVPDPWUUD::

↑ VPDPWUUDS: Multiply WORDs and accumulate results to DWORD.
Reference: EVEX.512.NP.0F38.W0 D3 /r VPDPWUUDS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5914

IihVPDPWUUDS:: PROC
  IiRequire AVX10
  IiAllowBroadcasting DWORD
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiEmitOpcode 0xD3
  IiDisp8EVEX FULL4
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.0F38.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.0F38.W0
  RET
 ENDP IihVPDPWUUDS::

↑ VRCPBF16: Compute reciprocals of packed 8|16|32 BF16.
Reference: EVEX.512.NP.MAP6.W0 4C /r VRCPBF16 zmm1{k1}{z}, zmm2/m512/m16bcst FULL MODRM.REG(w) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5657

IihVRCPBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x4C
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.mem:
.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVRCPBF16::

↑ VREDUCEBF16: Extract the reduced argument of BF16.
Reference: EVEX.512.F2.0F3A.W0 56 /r /ib VREDUCEBF16 zmm1{k1}{z}, zmm2/m512/m16bcst, imm8 FULL MODRM.REG(w) MODRM.R/M(r) IMM8(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5719

IihVREDUCEBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x56
  IiEmitImm Operand3, BYTE
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.ymm.ymm.imm:
.ymm.mem.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
 ENDP IihVREDUCEBF16::

↑ VRNDSCALEBF16: Round BF16.
Reference: EVEX.512.F2.0F3A.W0 08 /r /ib VRNDSCALEBF16 zmm1{k1}{z}, zmm2/m512/m16bcst, imm8 FULL MODRM.REG(w) MODRM.R/M(r) IMM8(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5719

IihVRNDSCALEBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x08
  IiEmitImm Operand3, BYTE
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
  IiEmitPrefix EVEX.128.F2.0F3A.W0
  RET
.ymm.ymm.imm:
.ymm.mem.imm:
  IiEmitPrefix EVEX.256.F2.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.F2.0F3A.W0
  RET
 ENDP IihVRNDSCALEBF16::

↑ VSCALEFBF16: Perform FP scale of packed BF16 in Operand2 by 2 power of BF16 in Operand3.
Reference: EVEX.512.NP.MAP6.W0 2C /r VSCALEFBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]

IihVSCALEFBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x2C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP6.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVSCALEFBF16::

↑ VRSQRTBF16: Reciprocals square-root of packed BF16.
Reference: EVEX.512.NP.MAP6.W0 4E /r VRSQRTBF16 zmm1{k1}{z}, zmm2/m512/m16bcst SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5653

IihVRSQRTBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x4E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
 IiEmitPrefix EVEX.128.NP.MAP6.W0
.ymm.ymm:
.ymm.mem:
 IiEmitPrefix EVEX.256.NP.MAP6.W0
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP6.W0
  RET
 ENDP IihVRSQRTBF16::

↑ VSQRTBF16: Square-root of packed BF16.
Reference: EVEX.512.66.MAP5.W0 51 /r VSQRTBF16 zmm1{k1}{z}, zmm2/m512/m16bcst SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5653

IihVSQRTBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x51
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
 IiEmitPrefix EVEX.128.66.MAP5.W0
.ymm.ymm:
.ymm.mem:
 IiEmitPrefix EVEX.256.66.MAP5.W0
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVSQRTBF16::

↑ VSUBBF16: Subtract packed BF16 values.
Reference: EVEX.512.66.MAP5.W0 5C /r VSUBBF16 zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.2]
Tested by: t5211

IihVSUBBF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x5C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVSUBBF16::

↑ VUCOMXSD: Unordered compare scalar FP64 values to ZF,PF,CF.
Reference: EVEX.LLIG.F2.0F.W1 2E /r VUCOMXSD xmm1, xmm2/m64{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5269

IihVUCOMXSD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Register=xmm, Swizzle=off
  IiDisp8EVEX SCALAR8
  IiEmitOpcode 0x2E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
.ymm.ymm:
.ymm.mem:
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.LLIG.F2.0F.W1
  RET
 ENDP IihVUCOMXSD::

↑ VUCOMXSH: Unordered compare scalar FP16 values to ZF,PF,CF.
Reference: EVEX.LLIG.F3.MAP5.W0 2E /r VUCOMXSH xmm1, xmm2/m16{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5269

IihVUCOMXSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVUCOMXSH::

↑ VUCOMXSS: Unordered compare FP32 values to ZF,PF,CF.
Reference: EVEX.LLIG.F3.0F.W0 2E /r VUCOMXSS xmm1, xmm2/m32{sae} SCALAR MODRM.REG(r) MODRM.R/M(r) N/A N/A
Documentation: [IntelAVX10.2]
Tested by: t5269

IihVUCOMXSS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Register=xmm, Swizzle=off
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0x2E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
.ymm.ymm:
.ymm.mem:
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.0F.W0
  RET
 ENDP IihVUCOMXSS::

↑ VADDPH: Add packed FP16 values.
Reference: EVEX.512.NP.MAP5.W0 58 /r VADDPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst{er} FULL MODRM.REG(w) VVVV(r) MODRM.R/M(r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVADDPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING,ROUND
  IiAllowBroadcasting WORD
  IiAllowRounding Register=zmm
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x58
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVADDPH::

↑ VADDSH: Add scalar FP16 value.
Reference: EVEX.LLIG.F3.MAP5.W0 58 /r VADDSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVADDSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x58
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVADDSH::

↑ VBCSTNEBF162PS: Load one BF16 Element from memory and Convert to FP32 Element With Broadcast.
Reference: VEX.128.F3.0F38.W0 B1 !(11):rrr:bbb VBCSTNEBF162PS xmm1, m16 VEX.256.F3.0F38.W0 B1 !(11):rrr:bbb VBCSTNEBF162PS ymm1, m16 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5248

IihVBCSTNEBF162PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB1
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.F3.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.F3.0F38.W0
  RET
 ENDP IihVBCSTNEBF162PS::

↑ VBCSTNESH2PS: Load one BF16 Element from memory and Convert to FP32 Element With Broadcast.
Reference: VEX.128.66.0F38.W0 B1 !(11):rrr:bbb VBCSTNESH2PS xmm1, m16 VEX.256.66.0F38.W0 B1 !(11):rrr:bbb VBCSTNESH2PS ymm1, m16 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5248

IihVBCSTNESH2PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB1
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0
  RET
 ENDP IihVBCSTNESH2PS::

↑ VCMPPH: Compare packed FP16 values.
Reference: EVEX.512.NP.0F3A.W0 C2 /r /ib VCMPPH k1{k2}, zmm2, zmm3/m512/m16bcst {sae}, imm8 Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
Documentation: [IntelAVX10.1]
Tested by: t5263

IihVCMPPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,SAE,BCST
  IiAllowSuppressing Operand=DH, Swizzle=off
  IiAllowBroadcasting WORD, Operand=DH
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xC2
  IiOpEn RVM
  IiModRM /r
  IiEmitImm Operand4, BYTE
  IiDispatchFormat krg.xmm.xmm.imm, krg.xmm.mem.imm, krg.ymm.ymm.imm, krg.ymm.mem.imm, krg.zmm.zmm.imm, krg.zmm.mem.imm
.krg.xmm.xmm.imm:
.krg.xmm.mem.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.krg.ymm.ymm.imm:
.krg.ymm.mem.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.krg.zmm.zmm.imm:
.krg.zmm.mem.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVCMPPH::

↑ VCMPSH: Compare scalar FP16 values.
Reference: EVEX.LLIG.F3.0F3A.W0 C2 /r /ib VCMPSH k1{k2}, xmm2, xmm3/m16{sae}, imm8 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
Documentation: [IntelAVX10.1]
Tested by: t5263

IihVCMPSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,SAE
  IiAllowSuppressing Operand=DH, Swizzle=off
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xC2
  IiOpEn RVM
  IiModRM /r
  IiEmitImm Operand4, BYTE
  IiDispatchFormat krg.xmm.xmm.imm, krg.xmm.mem.imm
.krg.xmm.xmm.imm:
.krg.xmm.mem.imm:
  IiEmitPrefix EVEX.LLIG.F3.0F3A.W0
  RET
 ENDP IihVCMPSH::

↑ VCOMISH: Compare scalar ordered FP16 values to EFLAGS.
Reference: EVEX.LLIG.NP.MAP5.W0 2F /r VCOMISH xmm1, xmm2/m16 {sae} Scalar ModRM:reg (r) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5268

IihVCOMISH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Swizzle=off
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2F
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
.ymm.ymm:
.ymm.mem:
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.LLIG.NP.MAP5.W0
  RET
 ENDP IihVCOMISH::

↑ VPCOMPRESSB: Compress packed BYTE values.
Reference: EVEX.512.66.0F38.W0 63 /r VPCOMPRESSB zmm1/m512{k1}{z}, zmm2 Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5272

IihVPCOMPRESSB:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR1
  IiEmitOpcode 0x63
  IiOpEn MR
  IiModRM /r
  IiDispatchFormat xmm.xmm, mem.xmm, ymm.ymm, mem.ymm, zmm.zmm, mem.zmm
.xmm.xmm:
.mem.xmm:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm:
.mem.ymm:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm:
.mem.zmm:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPCOMPRESSB::

↑ VPCOMPRESSW: Compress packet WORD values.
Reference: EVEX.512.66.0F38.W1 63 /r VPCOMPRESSW zmm1/m512{k1}{z}, zmm2 Tuple1 Scalar ModRM:r/m (w) ModRM:reg (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5272

IihVPCOMPRESSW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x63
  IiOpEn MR
  IiModRM /r
  IiDispatchFormat xmm.xmm, mem.xmm, ymm.ymm, mem.ymm, zmm.zmm, mem.zmm
.xmm.xmm:
.mem.xmm:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm:
.mem.ymm:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm:
.mem.zmm:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPCOMPRESSW::

↑ VCVTDQ2PH: Convert Packed Signed Doubleword Integers to Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 5B /r VCVTDQ2PH ymm1{k1}{z}, zmm2/m512/m32bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5221

IihVCVTDQ2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x5B
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, xmm.mem, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  RET
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.xmm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTDQ2PH::

↑ VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
Reference: EVEX.512.F2.0F38.W0 72 /r VCVTNE2PS2BF16 zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNE2PS2BF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,ZEROING,MASK
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x72
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W0
  RET
 ENDP IihVCVTNE2PS2BF16::

↑ VCVTNEEBF162PS: Convert Even Elements of Packed BF16 Values to FP32 Values.
Reference: VEX.256.F3.0F38.W0 B0 !(11):rrr:bbb VCVTNEEBF162PS ymm1, m256 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNEEBF162PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB0
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.F3.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.F3.0F38.W0
  RET
 ENDP IihVCVTNEEBF162PS::

↑ VCVTNEOBF162PS: Convert Odd Elements of Packed BF16 Values to FP32 Values.
Reference: VEX.256.F2.0F38.W0 B0 !(11):rrr:bbb VCVTNEOBF162PS ymm1, m256 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNEOBF162PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB0
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.F2.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.F2.0F38.W0
  RET
 ENDP IihVCVTNEOBF162PS::

↑ VCVTNEEPH2PS: Convert Even Elements of Packed FP16 Values to FP32 Values.
Reference: VEX.256.66.0F38.W0 B0 !(11):rrr:bbb VCVTNEEPH2PS ymm1, m256 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNEEPH2PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB0
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0
  RET
 ENDP IihVCVTNEEPH2PS::

↑ VCVTNEOPH2PS: Convert Odd Elements of Packed FP16 Values to FP32 Values.
Reference: VEX.256.NP.0F38.W0 B0 !(11):rrr:bbb VCVTNEOPH2PS ymm1, m256 N/A ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNEOPH2PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA
  IiEmitOpcode 0xB0
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, ymm.mem
.xmm.mem:
  IiEmitPrefix VEX.128.NP.0F38.W0
  RET
.ymm.mem:
  IiEmitPrefix VEX.256.NP.0F38.W0
  RET
 ENDP IihVCVTNEOPH2PS::

↑ VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
Reference: VEX.256.F3.0F38.W0 72 /r EVEX.512.F3.0F38.W0 72 /r VCVTNEPS2BF16 ymm1{k1}{z}, zmm2/m512/m32bcst Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5223

IihVCVTNEPS2BF16:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x72
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.mem, ymm.zmm
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix VEX.128.F3.0F38.W0, EVEX.128.F3.0F38.W0
  RET
.xmm.ymm:
  IiEmitPrefix VEX.256.F3.0F38.W0, EVEX.256.F3.0F38.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVCVTNEPS2BF16::

↑ VCVTPD2PH: Convert Packed Double Precision FP Values to Packed FP16 Values.
Reference: EVEX.512.66.MAP5.W1 5A /r VCVTPD2PH xmm1{k1}{z}, zmm2/m512/m64bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5225

IihVCVTPD2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST,MASK,ZEROING,ROUND
  IiAllowBroadcasting QWORD
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x5A
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.ymm, xmm.zmm, xmm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:, ZWORD=.xmm.zmm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEncoding DATA=OWORD
  IiEmitPrefix EVEX.128.66.MAP5.W1
  RET
.xmm.ymm:
  IiEncoding DATA=YWORD
  IiEmitPrefix EVEX.256.66.MAP5.W1
  RET
.xmm.zmm:
  IiEncoding DATA=ZWORD
  IiEmitPrefix EVEX.512.66.MAP5.W1
  RET
 ENDP IihVCVTPD2PH::

↑ VCVTPH2DQ: Convert Packed FP16 Values to Signed Doubleword Integers.
Reference: EVEX.512.66.MAP5.W0 5B /r VCVTPH2DQ zmm1{k1}{z}, ymm2/m256/m16bcst {er} Half ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5227

IihVCVTPH2DQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting WORD
  IiAllowRounding Operand=DL, Register=ymm
  IiDisp8EVEX HALF2
  IiEmitOpcode 0x5B
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPH2DQ::

↑ VCVTPH2PD: Convert Packed FP16 Values to FP64 Values.
Reference: EVEX.512.NP.MAP5.W0 5A /r VCVTPH2PD zmm1{k1}{z}, xmm2/m128/m16bcst {sae} Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5227

IihVCVTPH2PD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting WORD
  IiDisp8EVEX QUARTER2
  IiEmitOpcode 0x5A
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.xmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTPH2PD::

↑ VCVTPH2PSX: Convert Packed FP16 Values to Single Precision Floating-Point Values.
Reference: EVEX.512.66.MAP6.W0 13 /r VCVTPH2PSX zmm1{k1}{z}, ymm2/m256 {sae} Half ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5227

IihVCVTPH2PSX:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiDisp8EVEX HALF2
  IiEmitOpcode 0x13
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVCVTPH2PSX::

↑ VCVTPH2QQ: Convert Packed FP16 Values to Signed Quadword Integer Values.
Reference: EVEX.512.66.MAP5.W0 7B /r VCVTPH2QQ zmm1{k1}{z}, xmm2/m128/m16bcst {er} Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPH2QQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DH, Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX QUARTER2
  IiEmitOpcode 0x7B
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.xmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPH2QQ::

↑ VCVTPH2UQQ: Convert Packed FP16 Values to Unsigned Quadword Integers.
Reference: EVEX.512.66.MAP5.W0 79 /r VCVTPH2UQQ zmm1{k1}{z}, xmm2/m128/m16bcst {er} Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPH2UQQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting WORD
  IiAllowRounding Operand=DH, Register=zmm
  IiDisp8EVEX QUARTER2
  IiEmitOpcode 0x79
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.xmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPH2UQQ::

↑ VCVTPH2UDQ: Convert Packed FP16 Values to Unsigned Doubleword Integers.
Reference: EVEX.512.NP.MAP5.W0 79 /r VCVTPH2UDQ zmm1{k1}{z}, ymm2/m256/m16bcst {er} Half ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPH2UDQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DH, Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX HALF2
  IiEmitOpcode 0x79
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTPH2UDQ::

↑ VCVTPH2UW: Convert Packed FP16 Values to Unsigned Word Integers.
Reference: EVEX.512.NP.MAP5.W0 7D /r VCVTPH2UW zmm1{k1}{z}, zmm2/m512/m16bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPH2UW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DL, Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTPH2UW::

↑ VCVTPH2W: Convert Packed FP16 Values to Signed Word Integers.
Reference: EVEX.512.66.MAP5.W0 7D /r VCVTPH2W zmm1{k1}{z}, zmm2/m512/m16bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPH2W:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPH2W::

↑ VCVTPS2PHX: Convert Packed Single Precision Floating-Point Values to Packed FP16 Values.
Reference: EVEX.512.66.MAP5.W0 1D /r VCVTPS2PHX ymm1{k1}{z}, zmm2/m512/m32bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5229

IihVCVTPS2PHX:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DL, Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x1D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.mem, ymm.zmm
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.xmm.ymm:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTPS2PHX::

↑ VCVTQQ2PH: Convert Packed Signed Quadword Integers to Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W1 5B /r VCVTQQ2PH xmm1{k1}{z}, zmm2/m512/m64bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTQQ2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DL, Register=zmm
  IiAllowBroadcasting QWORD
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x5B
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.mem, xmm.xmm, xmm.ymm, xmm.zmm
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:, ZWORD=.xmm.zmm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W1
  RET
.xmm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W1
  RET
.xmm.zmm:
  IiEmitPrefix EVEX.512.NP.MAP5.W1
  RET
 ENDP IihVCVTQQ2PH::

↑ VCVTSD2SH: Convert Low FP64 Value to an FP16 Value.
Reference: EVEX.LLIG.F2.MAP5.W1 5A /r VCVTSD2SH xmm1{k1}{z}, xmm2, xmm3/m64 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSD2SH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR8
  IiEmitOpcode 0x5A
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.F2.MAP5.W1
  RET
 ENDP IihVCVTSD2SH::

↑ VCVTSH2SD: Convert Low FP16 Value to an FP64 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 5A /r VCVTSH2SD xmm1{k1}{z}, xmm2, xmm3/m16 {sae} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSH2SD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR8
  IiEmitOpcode 0x5A
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVCVTSH2SD::

↑ VCVTSI2SH: Convert a Signed Doubleword/Quadword Integer to an FP16 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 2A /r VCVTSI2SH xmm1, xmm2, r32/m32{er} EVEX.LLIG.F3.MAP5.W1 2A /r VCVTSI2SH xmm1, xmm2, r64/m64{er Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSI2SH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,ROUND
  IiEmitOpcode 0x2A
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.mem:
  IiDispatchData DWORD=.xmm.xmm.r32:, QWORD=.xmm.xmm.r64:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm.r32:
  IiEncoding DATA=DWORD
  IiDisp8EVEX SCALAR4
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.xmm.xmm.r64:
  IiEncoding DATA=QWORD
  IiDisp8EVEX SCALAR8
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTSI2SH::

↑ VCVTSH2SI: Convert Low FP16 Value to Signed Integer.
Reference: EVEX.LLIG.F3.MAP5.W0 2D /r VCVTSH2SI r32, xmm1/m16 {er} EVEX.LLIG.F3.MAP5.W1 2D /r VCVTSH2SI r64, xmm1/m16 {er} Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSH2SI:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,ROUND
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEncoding DATA=DWORD
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEncoding DATA=QWORD
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTSH2SI::

↑ VCVTSH2SS: Convert Low FP16 Value to FP32 Value.
Reference: EVEX.LLIG.NP.MAP6.W0 13 /r VCVTSH2SS xmm1{k1}{z}, xmm2, xmm3/m16 {sae} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSH2SS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x13
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.NP.MAP6.W0
  RET
 ENDP IihVCVTSH2SS::

↑ VCVTSH2USI: Convert Low FP16 Value to Unsigned Integer.
Reference: EVEX.LLIG.F3.MAP5.W0 79 /r VCVTSH2USI r32, xmm1/m16 {er} EVEX.LLIG.F3.MAP5.W1 79 /r VCVTSH2USI r64, xmm1/m16 {er} Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5231

IihVCVTSH2USI:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,ROUND
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x79
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEncoding DATA=DWORD
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEncoding DATA=QWORD
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTSH2USI::

↑ VCVTSS2SH: Convert Low FP32 Value to an FP16 Value.
Reference: EVEX.LLIG.NP.MAP5.W0 1D /r VCVTSS2SH xmm1{k1}{z}, xmm2, xmm3/m32 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5233

IihVCVTSS2SH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowBroadcasting DWORD
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0x1D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEncoding DATA=DWORD
  IiEmitPrefix EVEX.LLIG.NP.MAP5.W0
  RET
 ENDP IihVCVTSS2SH::

↑ VCVTSS2USI: Convert Scalar Single Precision Floating-Point Value to Unsigned Doubleword Integer.
Reference: EVEX.LLIG.F3.0F.W0 79 /r VCVTSS2USI r32, xmm1/m32{er} EVEX.LLIG.F3.0F.W1 79 /r VCVTSS2USI r64, xmm1/m32{er} Tuple1 Fixed ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5233

IihVCVTSS2USI:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,ROUND
  IiEmitOpcode 0x79
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEncoding DATA=DWORD
  IiDisp8EVEX SCALAR4
  IiEmitPrefix EVEX.LLIG.F3.0F.W0
  RET
.r64.xmm:
.r64.mem:
  IiEncoding DATA=QWORD
  IiDisp8EVEX SCALAR8
  IiEmitPrefix EVEX.LLIG.F3.0F.W1
  RET
 ENDP IihVCVTSS2USI::

↑ VCVTTPH2DQ: Convert with Truncation Packed FP16 Values to Signed Doubleword Integers.
Reference: EVEX.512.F3.MAP5.W0 5B /r VCVTTPH2DQ zmm1{k1}{z}, ymm2/m256/m16bcst {sae} Half ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5235

IihVCVTTPH2DQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting WORD
  IiDisp8EVEX HALF2
  IiAllowSuppressing
  IiEmitOpcode 0x5B
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  IiEncoding DATA=QWORD
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F3.MAP5.W0
  IiEncoding DATA=OWORD
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F3.MAP5.W0
  IiEncoding DATA=YWORD
  RET
 ENDP IihVCVTTPH2DQ::

↑ VCVTTPH2UDQ: Convert with Truncation Packed FP16 Values to Unsigned Doubleword Integers.
Reference: EVEX.512.NP.MAP5.W0 78 /r VCVTTPH2UDQ zmm1{k1}{z}, ymm2/m256/m16bcst {sae} Half ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5235

IihVCVTTPH2UDQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting WORD
  IiDisp8EVEX HALF2
  IiAllowSuppressing
  IiEmitOpcode 0x78
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.ymm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  IiEncoding DATA=DWORD
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  IiEncoding DATA=QWORD
  RET
.zmm.ymm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  IiEncoding DATA=OWORD
  RET
 ENDP IihVCVTTPH2UDQ::

↑ VCVTTPH2QQ: Convert with Truncation Packed FP16 Values to Signed Quadword Integers.
Reference: EVEX.512.66.MAP5.W0 7A /r VCVTTPH2QQ zmm1{k1}{z}, xmm2/m128/m16bcst {sae} Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5235

IihVCVTTPH2QQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowBroadcasting WORD
  IiDisp8EVEX QUARTER2
  IiEmitOpcode 0x7A
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  IiEncoding DATA=DWORD
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  IiEncoding DATA=QWORD
  RET
.zmm.xmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  IiEncoding DATA=OWORD
  RET
 ENDP IihVCVTTPH2QQ::

↑ VCVTTPH2UQQ: Convert with Truncation Packed FP16 Values to Unsigned Quadword Integers.
Reference: EVEX.512.66.MAP5.W0 78 /r VCVTTPH2UQQ zmm1{k1}{z}, xmm2/m128/m16bcst {sae} Quarter ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5235

IihVCVTTPH2UQQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Operand=DH, Swizzle=no
  IiAllowBroadcasting WORD
  IiDisp8EVEX QUARTER2
  IiEmitOpcode 0x78
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.xmm, ymm.mem, zmm.xmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  IiEncoding DATA=DWORD
  RET
.ymm.xmm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  IiEncoding DATA=QWORD
  RET
.zmm.xmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  IiEncoding DATA=OWORD
  RET
 ENDP IihVCVTTPH2UQQ::

↑ VCVTTPH2UW: Convert Packed FP16 Values to Unsigned Word Integers.
Reference: EVEX.512.NP.MAP5.W0 7C /r VCVTTPH2UW zmm1{k1}{z}, zmm2/m512/m16bcst {sae} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5235

IihVCVTTPH2UW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Operand=DH, Swizzle=no
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7C
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVCVTTPH2UW::

↑ VCVTTPH2W: Convert Packed FP16 Values to Signed Word Integers.
Reference: EVEX.512.66.MAP5.W0 7C /r VCVTTPH2W zmm1{k1}{z}, zmm2/m512/m16bcst {sae} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTTPH2W:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Operand=DH, Swizzle=no
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7C
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP5.W0
  RET
 ENDP IihVCVTTPH2W::

↑ VCVTTSH2SI: Convert with Truncation Low FP16 Value to a Signed Integer.
Reference: EVEX.LLIG.F3.MAP5.W0 2C /r VCVTTSH2SI r32, xmm1/m16 {sae} EVEX.LLIG.F3.MAP5.W1 2C /r VCVTTSH2SI r64, xmm1/m16 {sae} Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTTSH2SI:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Swizzle=no
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2C
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTTSH2SI::

↑ VCVTTSH2USI: Convert with Truncation Low FP16 Value to an Unsigned Integer.
Reference: EVEX.LLIG.F3.MAP5.W0 78 /r VCVTTSH2USI r32, xmm1/m16 {sae} EVEX.LLIG.F3.MAP5.W1 78 /r VCVTTSH2USI r64, xmm1/m16 {sae} Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTTSH2USI:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Swizzle=no
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x78
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat r32.xmm, r32.mem, r64.xmm, r64.mem
.r32.xmm:
.r32.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.r64.xmm:
.r64.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
 ENDP IihVCVTTSH2USI::

↑ VCVTUSQ2PH: Convert Packed Unsigned Doubleword Integers to Packed FP16 Values.
Reference: EVEX.512.F2.MAP5.W0 7A /r VCVTUDQ2PH ymm1{k1}{z}, zmm2/m512/m32bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTUDQ2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x7A
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, ymm.zmm, ymm.mem
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.xmm.ymm
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.ymm.zmm:
.ymm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTUDQ2PH::

↑ VCVTUSQ2PH: Convert Packed Unsigned Quadword Integers to Packed FP16 Values.
Reference: EVEX.512.F2.MAP5.W1 7A /r VCVTUQQ2PH xmm1{k1}{z}, zmm2/m512/m64bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTUQQ2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting QWORD
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x7A
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, xmm.ymm, xmm.zmm
.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.MAP5.W1
  RET
.xmm.ymm
  IiEmitPrefix EVEX.256.F2.MAP5.W1
  RET
.xmm.zmm:
  IiEmitPrefix EVEX.512.F2.MAP5.W1
  RET
.xmm.mem:
  IiDispatchData OWORD=.xmm.xmm:, YWORD=.xmm.ymm:, ZWORD=.xmm.zmm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
 ENDP IihVCVTUQQ2PH::

↑ VCVTUSQ2PH: Convert Unsigned Doubleword Integer to an FP16 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 7B /r VCVTUSI2SH xmm1, xmm2, r32/m32{er} EVEX.LLIG.F3.MAP5.W1 7B /r VCVTUSI2SH xmm1, xmm2, r64/m64{er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5219

IihVCVTUSI2SH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,ROUND
  IiAllowRounding Register=xmm, Operand=DL
  IiEmitOpcode 0x7B
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.r32, xmm.xmm.r64, xmm.xmm.mem
.xmm.xmm.r32:
  IiEncoding DATA=DWORD
  IiDisp8EVEX SCALAR4
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
.xmm.xmm.r64:
  IiEncoding DATA=QWORD
  IiDisp8EVEX SCALAR8
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W1
  RET
.xmm.xmm.mem:
  IiDispatchData DWORD=.xmm.xmm.r32:, QWORD=.xmm.xmm.r64:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
 ENDP IihVCVTUSI2SH::

↑ VCVTUW2PH: Convert Packed Unsigned Word Integers to FP16 Values.
Reference: EVEX.512.F2.MAP5.W0 7D /r VCVTUW2PH zmm1{k1}{z}, zmm2/m512/m16bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5225

IihVCVTUW2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm, Operand=DL
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP5.W0
  RET
 ENDP IihVCVTUW2PH::

↑ VCVTW2PH: Convert Packed Signed Word Integers to FP16 Values.
Reference: EVEX.512.F3.MAP5.W0 7D /r VCVTW2PH zmm1{k1}{z}, zmm2/m512/m16bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5225

IihVCVTW2PH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm, Operand=DL
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x7D
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.F3.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.F3.MAP5.W0
  RET
 ENDP IihVCVTW2PH::

↑ VDIVPH: Divide Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 5E /r VDIVPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVDIVPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm, Operand=DL
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x5E
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVDIVPH::

↑ VDIVSH: Divide Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP5.W0 5E /r VDIVSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVDIVSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm, Operand=DL
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x5E
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
 ENDP IihVDIVSH::

↑ VDPBF16PS: Dot Product of BF16 Pairs Accumulated Into Packed Single Precision.
Reference: EVEX.512.F3.0F38.W0 52 /r VDPBF16PS zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5912

IihVDPBF16PS:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x52
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F3.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F3.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.0F38.W0
  RET
 ENDP IihVDPBF16PS::

↑ VFCMADDCPH: Complex Multiply and Accumulate FP16 Values.
Reference: EVEX.512.F2.MAP6.W0 56 /r VFCMADDCPH zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4701

IihVFCMADDCPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x56
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP6.W0
  RET
 ENDP IihVFCMADDCPH::

↑ VFMADDCPH: Complex Multiply and Accumulate FP16 Values.
Reference: EVEX.512.F3.MAP6.W0 56 /r VFMADDCPH zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4701

IihVFMADDCPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=xmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x56
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F3.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.MAP6.W0
  RET
 ENDP IihVFMADDCPH::

↑ VFCMADDCSH: Complex Multiply and Accumulate Scalar FP16 Values.
Reference: EVEX.LLIG.F2.MAP6.W0 57 /r VFCMADDCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4701

IihVFCMADDCSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0x57
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F2.MAP6.W0
  RET
 ENDP IihVFCMADDCSH::

↑ VFMADDCSH: Complex Multiply and Accumulate Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP6.W0 57 /r VFMADDCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4701

IihVFMADDCSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0x57
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP6.W0
  RET
 ENDP IihVFMADDCSH::

↑ VFCMULCPH: Complex Multiply FP16 Values.
Reference: EVEX.512.F2.MAP6.W0 D6 /r VFCMULCPH zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4703

IihVFCMULCPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD6
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F2.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F2.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F2.MAP6.W0
  RET
 ENDP IihVFCMULCPH::

↑ VFMULCPH: Complex Multiply FP16 Values.
Reference: EVEX.512.F3.MAP6.W0 D6 /r VFMULCPH zmm1{k1}{z}, zmm2, zmm3/m512/m32bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4703

IihVFMULCPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xD6
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.F3.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.F3.MAP6.W0
  RET
 ENDP IihVFMULCPH::

↑ VFCMULCSH: Complex Multiply Scalar FP16 Values.
Reference: EVEX.LLIG.F2.MAP6.W0 D7 /r VFCMULCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4703

IihVFCMULCSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0xD7
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F2.MAP6.W0
  RET
 ENDP IihVFCMULCSH::

↑ VFMULCSH: Complex Multiply Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP6.W0 D7 /r VFMULCSH xmm1{k1}{z}, xmm2, xmm3/m32 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4703

IihVFMULCSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR4
  IiEmitOpcode 0xD7
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP6.W0
  RET
 ENDP IihVFMULCSH::

↑ VFMADD132SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 99 /r VFMADD132SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFMADD132SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x99
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMADD132SH::

↑ VFMADD213SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 A9 /r VFMADD213SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFMADD213SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xA9
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMADD213SH::

↑ VFMADD231SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 B9 /r VFMADD231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFMADD231SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xB9
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMADD231SH::

↑ VFNMADD132SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 9D /r VFNMADD132SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFNMADD132SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x9D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMADD132SH::

↑ VFNMADD213SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 AD /r VFNMADD213SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFNMADD213SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xAD
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMADD213SH::

↑ VFNMADD231SH: Fused Multiply-Add of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 BD /r VFNMADD231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4710

IihVFNMADD231SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xBD
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMADD231SH::

↑ VFMSUB132SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 9B /r VFMSUB132SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFMSUB132SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x9B
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMSUB132SH::

↑ VFMSUB213SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 AB /r VFMSUB213SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFMSUB213SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xAB
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMSUB213SH::

↑ VFMSUB231SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 BB /r VFMSUB231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFMSUB231SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xBB
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFMSUB231SH::

↑ VFNMSUB132SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 9F /r VFNMSUB132SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFNMSUB132SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x9F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMSUB132SH::

↑ VFNMSUB213SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 AF /r VFNMSUB213SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFNMSUB213SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xAF
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMSUB213SH::

↑ VFNMSUB231SH: Fused Multiply-Subtract of Scalar FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 BF /r VFNMSUB231SH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (r, w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4715

IihVFNMSUB231SH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0xBF
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVFNMSUB231SH::

↑ VFMADD132PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 98 /r VFMADD132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFMADD132PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x98
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMADD132PH::

↑ VFMADD213PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 A8 /r VFMADD213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFMADD213PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xA8
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMADD213PH::

↑ VFMADD231PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 B8 /r VFMADD231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFMADD231PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xB8
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMADD231PH::

↑ VFNMADD132PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 9C /r VFNMADD132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFNMADD132PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x9C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMADD132PH::

↑ VFNMADD213PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 AC /r VFNMADD213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFNMADD213PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xAC
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMADD213PH::

↑ VFNMADD231PH: Fused Multiply-Add of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 BC /r VFNMADD231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4720

IihVFNMADD231PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xBC
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMADD231PH::

↑ VFMSUB132PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 9A /r VFMSUB132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFMSUB132PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x9A
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMSUB132PH::

↑ VFMSUB213PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 AA /r VFMSUB213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFMSUB213PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xAA
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMSUB213PH::

↑ VFMSUB231PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 BA /r VFMSUB231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFMSUB231PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xBA
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFMSUB231PH::

↑ VFNMSUB132PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 9E /r VFNMSUB132PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFNMSUB132PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x9E
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMSUB132PH::

↑ VFNMSUB213PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 AE /r VFNMSUB213PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFNMSUB213PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xAE
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMSUB213PH::

↑ VFNMSUB231PH: Fused Multiply-Subtract of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 BE /r VFNMSUB231PH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4725

IihVFNMSUB231PH:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0xBE
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVFNMSUB231PH::

↑ VFMADDSUB132PS: Fused Multiply-Alternating Add/Subtract of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 96 /r VFMADDSUB132PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4730

IihVFMADDSUB132PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x96
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMADDSUB132PS::

↑ VFMADDSUB213PS: Fused Multiply-Alternating Add/Subtract of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 A6 /r VFMADDSUB213PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4730

IihVFMADDSUB213PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xA6
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMADDSUB213PS::

↑ VFMADDSUB231PS: Fused Multiply-Alternating Add/Subtract of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 B6 /r VFMADDSUB231PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4730

IihVFMADDSUB231PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xB6
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMADDSUB231PS::

↑ VFMSUBADD132PS: Fused Multiply-Alternating Subtract/Add of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 97 /r VFMSUBADD132PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4735

IihVFMSUBADD132PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x97
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMSUBADD132PS::

↑ VFMSUBADD213PS: Fused Multiply-Alternating Subtract/Add of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 A7 /r VFMSUBADD213PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4735

IihVFMSUBADD213PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xA7
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMSUBADD213PS::

↑ VFMSUBADD231PS: Fused Multiply-Alternating Subtract/Add of Packed Single Precision Floating-Point Values.
Reference: (E)VEX.512.66.0F38.W0 B7 /r VFMSUBADD231PS zmm1, zmm2, zmm3/m512/m32bcst{er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4735

IihVFMSUBADD231PS:: PROC
  IiRequire AVX10,FMA
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0xB7
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0, EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.66.0F38.W0, EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
 ENDP IihVFMSUBADD231PS::

↑ VFPCLASSPH: Test Types of Packed FP16 Values.
Reference: EVEX.512.NP.0F3A.W0 66 /r /ib VFPCLASSPH k1{k2}, zmm1/m512/m16bcst, imm8 Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4750

IihVFPCLASSPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,BCST
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x66
  IiOpEn RM
  IiModRM /r
  IiEmitImm Operand3, BYTE
  IiDispatchFormat krg.xmm.imm, krg.ymm.imm, krg.zmm.imm, krg.mem.imm
.krg.mem.imm:
  IiDispatchData OWORD=.krg.xmm.imm:, YWORD=.krg.ymm.imm:, ZWORD=.krg.zmm.imm:
  IiAbort '6730' ; Operand size could not be determined, please use DATA= modifier.
.krg.xmm.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.krg.ymm.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.krg.zmm.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVFPCLASSPH::

↑ VFPCLASSSH: Test Types of Scalar FP16 Values.
Reference: EVEX.LLIG.NP.0F3A.W0 67 /r /ib VFPCLASSSH k1{k2}, xmm1/m16, imm8 Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4750

IihVFPCLASSSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK
  IiEncoding DATA=WORD
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x67
  IiOpEn RM
  IiModRM /r
  IiEmitImm Operand3, BYTE
  IiDispatchFormat krg.xmm.imm, krg.mem.imm
.krg.xmm.imm:
.krg.mem.imm:
  IiEmitPrefix EVEX.LLIG.NP.0F3A.W0
  RET
 ENDP IihVFPCLASSSH::

↑ VGETEXPPH: Convert Exponents of Packed FP16 Values to FP16 Values.
Reference: EVEX.512.66.MAP6.W0 42 /r VGETEXPPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t4752

IihVGETEXPPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,BCST,SAE
  IiAllowSuppressing Register=zmm, Swizzle=off
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x42
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm:
.zmm.mem;
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVGETEXPPH::

↑ VGETEXPSH: Convert Exponents of Scalar FP16 Values to FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 43 /r VGETEXPSH xmm1{k1}{z}, xmm2, xmm3/m16 {sae} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4752

IihVGETEXPSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiAllowSuppressing Register=xmm, Swizzle=off
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x43
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVGETEXPSH::

↑ VGETMANTPH: Extract FP16 Vector of Normalized Mantissas from FP16 Vector.
Reference: EVEX.512.NP.0F3A.W0 26 /r /ib VGETMANTPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8 Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4754

IihVGETMANTPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,BCST,SAE
  IiAllowSuppressing Operand=DH, Register=zmm, Swizzle=off
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x26
  IiOpEn RM
  IiModRM /r
  IiEmitImm Operand3, BYTE, Max=15
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, zmm.zmm.imm, zmm.mem.imm
.xmm.xmm.imm:
.xmm.mem.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.ymm.ymm.imm:
.ymm.mem.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVGETMANTPH::

↑ VGETMANTSH: Extract FP16 of Normalized Mantissa from FP16 Scalar.
Reference: EVEX.LLIG.NP.0F3A.W0 27 /r /ib VGETMANTSH xmm1{k1}{z}, xmm2, xmm3/m16 {sae}, imm8 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
Documentation: [IntelAVX10.1]
Tested by: t4754

IihVGETMANTSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=xmm, Swizzle=off
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x27
  IiOpEn RVM
  IiModRM /r
  IiEmitImm Operand4, BYTE
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
  IiEmitPrefix EVEX.LLIG.NP.0F3A.W0
  RET
 ENDP IihVGETMANTSH::

↑ VMAXPH: Return Maximum of Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 5F /r VMAXPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {sae} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5215

IihVMAXPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Swizzle=no
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x5F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
 ENDP IihVMAXPH::

↑ VMINPH: Return Minimum of Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 5D /r Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5215

IihVMINPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Swizzle=no
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x5D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
 ENDP IihVMINPH::

↑ VMAXSH: Return Maximum of Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP5.W0 5F /r VMAXSH xmm1{k1}{z}, xmm2, xmm3/m16 {sae} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5215

IihVMAXSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiAllowSuppressing Register=xmm, Swizzle=no
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x5F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVMAXSH::

↑ VMINSH: Return Minimum of Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP5.W0 5D /r VMINSH xmm1{k1}{z}, xmm2, xmm3/m16 {sae} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5215

IihVMINSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,SAE
  IiAllowSuppressing Register=xmm, Swizzle=no
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x5D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVMINSH::

↑ VMOVSH: —Move Scalar FP16 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 10 /r VMOVSH xmm1{k1}{z}, m16 VMOVSH xmm1{k1}{z}, xmm2, xmm3 EVEX.LLIG.F3.MAP5.W0 11 /r VMOVSH m16{k1}, xmm1 VMOVSH xmm1{k1}{z}, xmm2, xmm3
Documentation: [IntelAVX10.1]
Tested by: t5472

IihVMOVSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,CODE,MASK,ZEROING
  IiDisp8EVEX SCALAR2
  IiEncoding DATA=WORD
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.mem, mem.xmm
.xmm.mem:
    IiOpEn RM
.10:IiEmitOpcode 0x10
    JMPS .12:
.mem.xmm:
    IiOpEn MR
.11:IiEmitOpcode 0x11
.12:IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
    RET
.xmm.xmm.xmm:
    IiDispatchCode LONG=.LONG
    IiEncoding CODE=SHORT
    IiOpEn RVM
    JMP .10:
.LONG:
    IiEncoding CODE=LONG
    IiOpEn MVR
    JMP .11:
 ENDP IihVMOVSH::

↑ VMULPH: Multiply Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 59 /r VMULPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVMULPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Register=zmm
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x59
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVMULPH::

↑ VMULSH: Multiply Scalar FP16 Values.
Reference: EVEX.LLIG.F3.MAP5.W0 59 /r VMULSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5211

IihVMULSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x59
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.F3.MAP5.W0
  RET
 ENDP IihVMULSH::

↑ VPEXPANDB: Expand Byte Values.
Reference: EVEX.512.66.0F38.W0 62 /r VPEXPANDB zmm1{k1}{z}, zmm2/mem512 Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5277

IihVPEXPANDB:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR1
  IiEmitOpcode 0x62
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPEXPANDB::

↑ VPEXPANDW: Expand Byte Values.
Reference: EVEX.512.66.0F38.W1 62 /r VPEXPANDW zmm1{k1}{z}, zmm2/mem512 Tuple1 Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5277

IihVPEXPANDW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x62
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPEXPANDW::

↑ VPSHLDVW: Concatenate and Variable Shift Packed Data Left Logical.
Reference: EVEX.512.66.0F38.W1 70 /r VPSHLDVW zmm1{k1}{z}, zmm2, zmm3/m512 Full Mem ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4529

IihVPSHLDVW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX FULLMEM
  IiEmitOpcode 0x70
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPSHLDVW::

↑ VPSHLDVD: Concatenate and Variable Shift Packed Data Left Logical.
Reference: EVEX.512.66.0F38.W0 71 /r VPSHLDVD zmm1{k1}{z}, zmm2, zmm3/m512bcst Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4529

IihVPSHLDVD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x71
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPSHLDVD::

↑ VPSHLDVQ: Concatenate and Variable Shift Packed Data Left Logical.
Reference: EVEX.512.66.0F38.W1 71 /r VPSHLDVQ zmm1{k1}{z}, zmm2, zmm3/m512bcst Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4529

IihVPSHLDVQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting QWORD
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x71
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPSHLDVQ::

↑ VPSHRDVW: Concatenate and Variable Shift Packed Data Right Logical.
Reference: EVEX.512.66.0F38.W1 72 /r VPSHRDVW zmm1{k1}{z}, zmm2, zmm3/m512 Full Mem ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4528

IihVPSHRDVW:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX FULLMEM
  IiEmitOpcode 0x72
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPSHRDVW::

↑ VPSHRDVD: Concatenate and Variable Shift Packed Data Right Logical.
Reference: EVEX.512.66.0F38.W0 73 /r VPSHRDVD zmm1{k1}{z}, zmm2, zmm3/m512bcst Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4528

IihVPSHRDVD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting DWORD
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x73
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPSHRDVD::

↑ VPSHRDVQ: Concatenate and Variable Shift Packed Data Right Logical.
Reference: EVEX.512.66.0F38.W1 73 /r VPSHRDVQ zmm1{k1}{z}, zmm2, zmm3/m512bcst Full ModRM:reg (r, w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4528

IihVPSHRDVQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting QWORD
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x73
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W1
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W1
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W1
  RET
 ENDP IihVPSHRDVQ::

↑ VPSHUFBITQMB: Shuffle Bits From Quadword Elements Using Byte Indexes Into Mask.
Reference: EVEX.512.66.0F38.W0 8F /r VPSHUFBITQMB k1{k2}, xmm2, xmm3/m128 Full Mem ModRM:reg (w) EVEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5649

IihVPSHUFBITQMB:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK
  IiDisp8EVEX FULLMEM
  IiEmitOpcode 0x8F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat krg.xmm.xmm, krg.xmm.mem, krg.ymm.ymm, krg.ymm.mem, krg.zmm.zmm, krg.zmm.mem
.krg.xmm.xmm:
.krg.xmm.mem:
  IiEmitPrefix EVEX.128.66.0F38.W0
  RET
.krg.ymm.ymm:
.krg.ymm.mem:
  IiEmitPrefix EVEX.256.66.0F38.W0
  RET
.krg.zmm.zmm:
.krg.zmm.mem:
  IiEmitPrefix EVEX.512.66.0F38.W0
  RET
 ENDP IihVPSHUFBITQMB::

↑ VRCPPH: Compute Reciprocals of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 4C /r VRCPPH zmm1{k1}{z}, zmm2/m512/m16bcst Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5657

IihVRCPPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST
  IiAllowBroadcasting WORD
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x4C
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.xmm:
.xmm.mem:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm:
.ymm.mem:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVRCPPH::

↑ VRCPSH: Compute Reciprocal of Scalar FP16 Value.
Reference: EVEX.LLIG.66.MAP6.W0 4D /r VRCPSH xmm1{k1}{z}, xmm2, xmm3/m16 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5657

IihVRCPSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x4D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVRCPSH::

↑ VREDUCEPH: Perform Reduction Transformation on Packed FP16 Values.
Reference: EVEX.512.NP.0F3A.W0 56 /r /ib VREDUCEPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8 Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5719

IihVREDUCEPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,BCST,MASK,SAE
  IiAllowSuppressing Operand=DH, Swizzle=Off
  IiAllowBroadcasting WORD, Operand=DH
  IiEmitOpcode 0x56
  IiDisp8EVEX FULL2
  IiEmitImm Operand3, BYTE
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, \
                   zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.ymm.mem.imm:
.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVREDUCEPH::

↑ VREDUCESH: Perform Reduction Transformation on Scalar FP16 Value.
Reference: EVEX.LLIG.NP.0F3A.W0 57 /r /ib VREDUCESH xmm1{k1}{z}, xmm2, xmm3/m16 {sae}, imm8 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
Documentation: [IntelAVX10.1]
Tested by: t5719

IihVREDUCESH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Register=xmm, Swizzle=Off
  IiAllowBroadcasting WORD, Operand=DH
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x57
  IiOpEn RM
  IiModRM /r
  IiEmitImm Operand4, BYTE
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.LLIG.NP.0F3A.W0
  RET
 ENDP IihVREDUCESH::

↑ VRNDSCALEPH: Round Packed FP16 Values to Include a Given Number of Fraction Bits.
Reference: EVEX.512.NP.0F3A.W0 08 /r /ib VRNDSCALEPH zmm1{k1}{z}, zmm2/m512/m16bcst {sae}, imm8 Full ModRM:reg (w) ModRM:r/m (r) imm8 (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5713

IihVRNDSCALEPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,BCST,SAE
  IiAllowSuppressing Operand=DH, Swizzle=Off
  IiAllowBroadcasting WORD, Operand=DH
  IiEmitOpcode 0x08
  IiDisp8EVEX FULL2
  IiEmitImm Operand3, BYTE
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm.imm, xmm.mem.imm, ymm.ymm.imm, ymm.mem.imm, \
                   zmm.zmm.imm, zmm.mem.imm
.xmm.mem.imm:
.xmm.xmm.imm:
  IiEmitPrefix EVEX.128.NP.0F3A.W0
  RET
.ymm.mem.imm:
.ymm.ymm.imm:
  IiEmitPrefix EVEX.256.NP.0F3A.W0
  RET
.zmm.zmm.imm:
.zmm.mem.imm:
  IiEmitPrefix EVEX.512.NP.0F3A.W0
  RET
 ENDP IihVRNDSCALEPH::

↑ VRNDSCALESH: Round Scalar FP16 Value to Include a Given Number of Fraction Bits.
Reference: EVEX.LLIG.NP.0F3A.W0 0A /r /ib VRNDSCALESH xmm1{k1}{z}, xmm2, xmm3/m16 {sae}, imm8 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) imm8 (r)
Documentation: [IntelAVX10.1]
Tested by: t5713

IihVRNDSCALESH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,SAE
  IiAllowSuppressing Operand=DH, Swizzle=Off
  IiEmitOpcode 0x0A
  IiDisp8EVEX SCALAR2
  IiEmitImm Operand4, BYTE
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.mem.imm:
.xmm.xmm.xmm.imm:
  IiEmitPrefix EVEX.LLIG.NP.0F3A.W0
  RET
 ENDP IihVRNDSCALESH::

↑ VRSQRTPH: Compute Reciprocals of Square Roots of Packed FP16 Values.
Reference: EVEX.512.66.MAP6.W0 4E /r VRSQRTPH zmm1{k1}{z}, zmm2/m512/m16bcs Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5653

IihVRSQRTPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,BCST
  IiAllowBroadcasting WORD, Operand=DL
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x4E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.mem:
.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVRSQRTPH::

↑ VRSQRTSH: —Compute Approximate Reciprocal of Square Root of Scalar FP16 Value.
Reference: EVEX.LLIG.66.MAP6.W0 4F /r VRSQRTSH xmm1{k1}{z}, xmm2, xmm3/m16 Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5653

IihVRSQRTSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x4F
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVRSQRTSH::

↑ VSCALEFPH: Scale Packed FP16 Values with FP16 Values.
Reference: EVEX.512.66.MAP6.W0 2C /r VSCALEFPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5711

IihVSCALEFPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,IMM,MASK,ZEROING,BCST,ROUND
  IiAllowRounding
  IiAllowBroadcasting WORD, Operand=DL
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x2C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.66.MAP6.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.66.MAP6.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.66.MAP6.W0
  RET
 ENDP IihVSCALEFPH::

↑ VSCALEFSH: Scale Scalar FP16 Values with FP16 Values.
Reference: EVEX.LLIG.66.MAP6.W0 2D /r VSCALEFSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5711

IihVSCALEFSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL,Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2D
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.66.MAP6.W0
  RET
 ENDP IihVSCALEFSH::

↑ VSHA512MSG1: Perform an Intermediate Calculation for the Next Four SHA512 Message Qword.
Reference: VEX.256.F2.0F38.W0 CC 11:rrr:bbb VSHA512MSG1 ymm1, xmm2
Documentation: [IntelAVX10.1]
Tested by: t4533

IihVSHA512MSG1:: PROC
  IiRequire AVX10,SHA
  IiEmitOpcode 0xCC
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat ymm.xmm
.ymm.xmm:
  IiEmitPrefix VEX.256.F2.0F38.W0
  RET
 ENDP IihVSHA512MSG1::

↑ VSHA512MSG2: Perform a Final Calculation for the Next Four SHA512 Message Qwords.
Reference: VEX.256.F2.0F38.W0 CD 11:rrr:bbb VSHA512MSG2 ymm1, ymm2
Documentation: [IntelAVX10.1]
Tested by: t4533

IihVSHA512MSG2:: PROC
  IiRequire AVX10,SHA
  IiEmitOpcode 0xCD
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat ymm.ymm
.ymm.ymm:
  IiEmitPrefix VEX.256.F2.0F38.W0
  RET
 ENDP IihVSHA512MSG2::

↑ VSHA512RNDS2: Perform Two Rounds of SHA512 Operation.
Reference: VEX.256.F2.0F38.W0 CB 11:rrr:bbb VSHA512RNDS2 ymm1, ymm2, xmm3
Documentation: [IntelAVX10.1]
Tested by: t4533

IihVSHA512RNDS2:: PROC
  IiRequire AVX10,SHA
  IiEmitOpcode 0xCB
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat ymm.ymm.xmm
.ymm.ymm.xmm:
  IiEmitPrefix VEX.256.F2.0F38.W0
  RET
 ENDP IihVSHA512RNDS2::

↑ VSM3MSG1: —Perform Initial Calculation for the Next Four SM3 Message Words.
Reference: VEX.128.NP.0F38.W0 DA /r VSM3MSG1 xmm1, xmm2, xmm3/m128
Documentation: [IntelAVX10.1]
Tested by: t4910

IihVSM3MSG1:: PROC
  IiRequire AVX10,SHA
  IiAllowModifier DATA,IMM
  IiEmitOpcode 0xDA
  IiOpEn RVM
  IiModRM /r
  IiEncoding DATA=OWORD
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.NP.0F38.W0
  RET
 ENDP IihVSM3MSG1::

↑ VSM3MSG2: Perform Final Calculation for the Next Four SM3 Message Words.
Reference: VEX.128.66.0F38.W0 DA /r VSM3MSG2 xmm1, xmm2, xmm3/m128
Documentation: [IntelAVX10.1]
Tested by: t4910

IihVSM3MSG2:: PROC
  IiRequire AVX10,SHA
  IiAllowModifier DATA
  IiEmitOpcode 0xDA
  IiOpEn RVM
  IiModRM /r
  IiEncoding DATA=OWORD
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.66.0F38.W0
  RET
 ENDP IihVSM3MSG2::

↑ VSM3RNDS2: Perform Two Rounds of SM3 Operation.
Reference: VEX.128.66.0F3A.W0 DE /r /ib VSM3RNDS2 xmm1, xmm2, xmm3/m128, imm8
Documentation: [IntelAVX10.1]
Tested by: t4910

IihVSM3RNDS2:: PROC
  IiRequire AVX10,SHA
  IiAllowModifier DATA,IMM
  IiEmitOpcode 0xDE
  IiOpEn RVM
  IiModRM /r
  IiEncoding DATA=OWORD
  IiEmitImm Operand4, BYTE
  IiDispatchFormat xmm.xmm.xmm.imm, xmm.xmm.mem.imm
.xmm.xmm.xmm.imm:
.xmm.xmm.mem.imm:
  IiEmitPrefix VEX.128.66.0F3A.W0
  RET
 ENDP IihVSM3RNDS2::

↑ VSM4KEY4: Perform Four Rounds of SM4 Key Expansion.
Reference: VEX.256.F3.0F38.W0 DA /r VSM4KEY4 ymm1, ymm2, ymm3/m256
Documentation: [IntelAVX10.1]
Tested by: t4910

IihVSM4KEY4:: PROC
  IiRequire AVX10,SHA
  IiAllowModifier DATA
  IiEmitOpcode 0xDA
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.F3.0F38.W0
  IiEncoding DATA=OWORD
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.F3.0F38.W0
  IiEncoding DATA=YWORD
  RET
 ENDP IihVSM4KEY4::

↑ VSM4RNDS4: Performs Four Rounds of SM4 Encryption.
Reference: VEX.256.F2.0F38.W0 DA /r VSM4RNDS4 ymm1, ymm2, ymm3/m256
Documentation: [IntelAVX10.1]
Tested by: t4910

IihVSM4RNDS4:: PROC
  IiRequire AVX10,SHA
  IiEmitOpcode 0xDA
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
.xmm.xmm.xmm:
.xmm.xmm.mem:
  IiEmitPrefix VEX.128.F2.0F38.W0
  IiEncoding DATA=OWORD
  RET
.ymm.ymm.ymm:
.ymm.ymm.mem:
  IiEmitPrefix VEX.256.F2.0F38.W0
  IiEncoding DATA=YWORD
  RET
 ENDP IihVSM4RNDS4::

↑ VSQRTPH: Compute Square Root of Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 51 /r VSQRTPH zmm1{k1}{z}, zmm2/m512/m16bcst {er} Full ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5653

IihVSQRTPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DL, Register=zmm
  IiAllowBroadcasting WORD, Operand=DL
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x51
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem, ymm.ymm, ymm.mem, zmm.zmm, zmm.mem
.xmm.mem:
.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.mem:
.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm:
.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVSQRTPH::

↑ VSQRTSH: Compute Square Root of Scalar FP16 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 51 /r VSQRTSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5653

IihVSQRTSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x51
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVSQRTSH::

↑ VSUBPH: Subtract Packed FP16 Values.
Reference: EVEX.512.NP.MAP5.W0 5C /r VSUBPH zmm1{k1}{z}, zmm2, zmm3/m512/m16bcst {er} Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5615

IihVSUBPH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,BCST,ROUND
  IiAllowRounding Operand=DL, Register=zmm
  IiAllowBroadcasting WORD, Operand=DL
  IiDisp8EVEX FULL2
  IiEmitOpcode 0x5C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem, zmm.zmm.zmm, zmm.zmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.128.NP.MAP5.W0
  RET
.ymm.ymm.mem:
.ymm.ymm.ymm:
  IiEmitPrefix EVEX.256.NP.MAP5.W0
  RET
.zmm.zmm.zmm:
.zmm.zmm.mem:
  IiEmitPrefix EVEX.512.NP.MAP5.W0
  RET
 ENDP IihVSUBPH::

↑ VSUBSH: Subtract Scalar FP16 Value.
Reference: EVEX.LLIG.F3.MAP5.W0 5C /r VSUBSH xmm1{k1}{z}, xmm2, xmm3/m16 {er} Scalar ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t5615

IihVSUBSH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,MASK,ZEROING,ROUND
  IiAllowRounding Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x5C
  IiOpEn RVM
  IiModRM /r
  IiDispatchFormat xmm.xmm.xmm, xmm.xmm.mem
.xmm.xmm.mem:
.xmm.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.F3.MAP5.W0
  RET
 ENDP IihVSUBSH::

↑ VUCOMISH: Unordered Compare Scalar FP16 Values and Set EFLAGS.
Reference: EVEX.LLIG.NP.MAP5.W0 2E /r VUCOMISH xmm1, xmm2/m16 {sae} Scalar ModRM:reg (w) ModRM:r/m (r) N/A N/A
Documentation: [IntelAVX10.1]
Tested by: t5268

IihVUCOMISH:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,SAE
  IiAllowSuppressing Operand=DL, Register=xmm
  IiDisp8EVEX SCALAR2
  IiEmitOpcode 0x2E
  IiOpEn RM
  IiModRM /r
  IiDispatchFormat xmm.xmm, xmm.mem
.xmm.mem:
.xmm.xmm:
  IiEmitPrefix EVEX.LLIG.NP.MAP5.W0
  RET
 ENDP IihVUCOMISH::

↑ VP2INTERSECTD: Compute Intersection Between DWORDS to a Pair of Mask Registers.
Reference: EVEX.NDS.512.F2.0F38.W0 68 /r VP2INTERSECTD k1+1, zmm2, zmm3/m512/m32bcs Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4760

IihVP2INTERSECTD:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST
  IiAllowBroadcasting DWORD, Operand=DL
  IiDisp8EVEX FULL4
  IiEmitOpcode 0x68
  IiOpEn RVM
  IiModRM /r
  IiEncoding DATA=DWORD
  IiDispatchFormat krg.xmm.xmm, krg.xmm.mem, krg.ymm.ymm, krg.ymm.mem, krg.zmm.zmm, krg.zmm.mem
.krg.xmm.mem:
.krg.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.0F38.W0
  RET
.krg.ymm.mem:
.krg.ymm.ymm:
  IiEmitPrefix EVEX.256.F2.0F38.W0
  RET
.krg.zmm.zmm:
.krg.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W0
  RET
 ENDP IihVP2INTERSECTD::

↑ VP2INTERSECTQ: Compute Intersection Between QWORDS to a Pair of Mask Registers.
Reference: EVEX.NDS.512.F2.0F38.W1 68 /r VP2INTERSECTQ k1+1, zmm2, zmm3/m512/m64bcs Full ModRM:reg (w) VEX.vvvv (r) ModRM:r/m (r) N/A
Documentation: [IntelAVX10.1]
Tested by: t4760

IihVP2INTERSECTQ:: PROC
  IiRequire AVX10
  IiAllowModifier DATA,BCST
  IiAllowBroadcasting QWORD, Operand=DL
  IiDisp8EVEX FULL8
  IiEmitOpcode 0x68
  IiOpEn RVM
  IiModRM /r
  IiEncoding DATA=QWORD
  IiDispatchFormat krg.xmm.xmm, krg.xmm.mem, krg.ymm.ymm, krg.ymm.mem, krg.zmm.zmm, krg.zmm.mem
.krg.xmm.mem:
.krg.xmm.xmm:
  IiEmitPrefix EVEX.128.F2.0F38.W1
  RET
.krg.ymm.mem:
.krg.ymm.ymm:
  IiEmitPrefix EVEX.256.F2.0F38.W1
  RET
.krg.zmm.zmm:
.krg.zmm.mem:
  IiEmitPrefix EVEX.512.F2.0F38.W1
  RET
 ENDP IihVP2INTERSECTQ::

  ENDPROGRAM iih

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