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# iim.htm
Enumerations
IimList
Group handlers
IimGroupSSE2
IimGroupSSE3
Instruction handlers
CVTPD2PI CVTPI2PD CVTPI2PS CVTPS2PI CVTTPD2PI CVTTPS2PI EMMS MASKMOVQ MOVDQ2Q MOVNTQ MOVQ2DQ PABSB PABSD PABSW PACKSSDW PACKSSWB PACKUSWB PADDB PADDD PADDQ PADDSB PADDSW PADDUSB PADDUSW PADDW PALIGNR PAND PANDN PAVGB PAVGW PCMPEQB PCMPEQD PCMPEQW PCMPGTB PCMPGTD PCMPGTW PEXTRW PHADDD PHADDSW PHADDW PHSUBD PHSUBSW PHSUBW PINSRW PMADDUBSW PMADDWD PMAXSW PMAXUB PMINSW PMINUB PMOVMSKB PMULHRSW PMULHUW PMULHW PMULLW PMULUDQ POR PSADBW PSHUFB PSHUFW PSIGNB PSIGND PSIGNW PSLLD PSLLQ PSLLW PSRAD PSRAW PSRLD PSRLQ PSRLW PSUBB PSUBD PSUBQ PSUBSB PSUBSW PSUBUSB PSUBUSW PSUBW PUNPCKHBW PUNPCKHDQ PUNPCKHWD PUNPCKLBW PUNPCKLDQ PUNPCKLWD PXOR

↑ IimHandlers
  assemble MMX multimedia machine instructions.
See also
  IiHandlers, [IntelVol2].

    iim PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
        INCLUDEHEAD euroasm.htm, \  Interface (structures, symbols and macros) of other modules used in this source.
                    ea.htm,eaopt.htm,exp.htm,ii.htm,msg.htm,pgm.htm,pgmopt.htm,sss.htm,stm.htm,sym.htm

    iim HEAD ; Start of module interface.

↑ %IimList
  enumerates machine instructions of this family which €ASM can assemble.
  Each instruction declared in `%IimList` requires the corresponding handler in this file.
See also
  DictLookupIi

    %IimList %SET \
    PSLLW, \
    PSLLD, \
    PSLLQ, \
    PSRAW, \
    PSRAD, \
    PSRLW, \
    PSRLD, \
    PSRLQ, \
    PUNPCKLBW, \
    PUNPCKLWD, \
    PUNPCKLDQ, \
    PACKSSWB, \
    PCMPGTB, \
    PCMPGTW, \
    PCMPGTD, \
    PACKUSWB, \
    PUNPCKHBW, \
    PUNPCKHWD, \
    PUNPCKHDQ, \
    PACKSSDW, \
    PCMPEQB, \
    PCMPEQW, \
    PCMPEQD, \
    PADDQ, \
    PMULLW, \
    PSUBUSB, \
    PSUBUSW, \
    PMINUB, \
    PAND, \
    PADDUSB, \
    PADDUSW, \
    PMAXUB, \
    PANDN, \
    PAVGB, \
    PAVGW, \
    PMULHUW, \
    PMULHW, \
    PSUBSB, \
    PSUBSW, \
    PMINSW, \
    POR, \
    PADDSB, \
    PADDSW, \
    PMAXSW, \
    PXOR, \
    PMULUDQ, \
    PMADDWD, \
    PSADBW, \
    PSUBB, \
    PSUBW, \
    PSUBD, \
    PSUBQ, \
    PADDB, \
    PADDW, \
    PADDD, \
    EMMS, \
    MASKMOVQ, \
    MOVNTQ , \
    PINSRW, \
    PMOVMSKB, \
    PSHUFW, \
    PEXTRW, \
    PALIGNR, \
    PSHUFB, \
    PHADDW, \
    PHADDD, \
    PHADDSW, \
    PMADDUBSW, \
    PHSUBW, \
    PHSUBD, \
    PHSUBSW, \
    PSIGNB, \
    PSIGNW, \
    PSIGND, \
    PMULHRSW, \
    PABSB, \
    PABSW, \
    PABSD, \
    CVTPI2PD, \
    CVTTPD2PI, \
    CVTPD2PI, \
    CVTPS2PI, \
    CVTPI2PS, \
    CVTTPS2PI, \
    MOVDQ2Q, \
    MOVQ2DQ, \

    ;

      ENDHEAD iim ; End of module interface.

↑ PSRLW
  Shift Packed Data Right Logical
Description
  PSRLW
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F71 /2 | 0x660F71 /2 | 0x0FD1 /r | 0x660FD1 /r
CPU
  PX+

    IimPSRLW:: PROC
        MOV CL,0xD1
        MOV EAX,iiPpgModRMd + 2<<28 ; ModRM /2                                                       ;; >>
    .W: MOV CH,0x71
        IiEncoding DATA=WORD
    .cc:IiEmitOpcode 0x0F
        IiDispatchFormat mmx.mmx, mmx.mem, mmx.imm, xmm.xmm, xmm.mem, xmm.imm
    .xmm.xmm:
    .xmm.mem:
         IiRequire SSE2
         IiEmitPrefix OTOGGLE
    .mmx.mmx:
    .mmx.mem:
         IiEmitOpcode ECX
         IiOpEn RM
         IiModRM /r
         RET
    .xmm.imm:
         IiRequire SSE2
         IiEmitPrefix OTOGGLE
    .mmx.imm:
         SHR ECX,8
         IiEmitOpcode ECX
         IiAllowModifier IMM
         IiOpEn M
         IiModRM EAX
         IiEmitImm Operand2, BYTE
         RET
     ENDP IimPSRLW::

↑ PSRLD
  Shift Double Quadword Right Logical
Description
  PSRLD
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F72 /2 | 0x660F72 /2 | 0x0FD2 /r | 0x660FD2 /r
CPU
  PX+

    IimPSRLD:: PROC
        MOV CL,0xD2
        MOV EAX,iiPpgModRMd + 2<<28 ; ModRM /2                                                      ;; >>
    .D: IiEncoding DATA=DWORD
        MOV CH,0x72
        JMP IimPSRLW.cc:
     ENDP IimPSRLD::

↑ PSRLQ
  Shift Packed Data Right Logical
Description
  PSRLQ
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F73 /2 | 0x660F73 /2 | 0x0FD3 /r | 0x660FD3 /r
CPU
  PX+

    IimPSRLQ:: PROC
        MOV CL,0xD3
        MOV EAX,iiPpgModRMd + 2<<28 ; ModRM /2                                                      ;; >>
    .Q: IiEncoding DATA=QWORD
        MOV CH,0x73
        JMP IimPSRLW.cc:
     ENDP IimPSRLQ::

↑ PSRAW
  Shift Packed Data Right Arithmetic
Description
  PSRAW
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F71 /4 | 0x660F71 /4 | 0x0FE1 /r | 0x660FE1 /r
CPU
  PX+

    IimPSRAW:: PROC
        MOV CL,0xE1
        MOV EAX,iiPpgModRMd + 4<<28  ; ModRM /4                                                     ;; >>
        JMP IimPSRLW.W:
     ENDP IimPSRAW::

↑ PSRAD
  Shift Packed Data Right Arithmetic
Description
  PSRAD
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F72 /4 | 0x660F72 /4 | 0x0FE2 /r | 0x660FE2 /r
CPU
  PX+

    IimPSRAD:: PROC
        MOV CL,0xE2
        MOV EAX,iiPpgModRMd + 4<<28  ; ModRM /4                                                     ;; >>
        JMP IimPSRLD.D:
     ENDP IimPSRAD::

↑ PSLLW
  Shift Packed Data Left Logical
Description
  PSLLW
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F71 /6 | 0x660F71 /6 | 0x0FF1 /r | 0x660FF1 /r
CPU
  PX+

    IimPSLLW:: PROC
        MOV CL,0xF1
        MOV EAX,iiPpgModRMd + 6<<28  ; ModRM /6                                                     ;; >>
        JMP IimPSRLW.W:
     ENDP IimPSLLW::

↑ PSLLD
  Shift Packed Data Left Logical
Description
  PSLLD
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F72 /6 | 0x660F72 /6 | 0x0FF2 /r | 0x660FF2 /r
CPU
  PX+

    IimPSLLD:: PROC
        MOV CL,0xF2
        MOV EAX,iiPpgModRMd + 6<<28  ; ModRM /6                                                     ;; >>
        JMP IimPSRLD.D:
     ENDP IimPSLLD::

↑ PSLLQ
  Shift Packed Data Left Logical
Description
  PSLLQ
Category
  mmx,shift
Operands
  Nq,Ib | Udq,Ib | Pq,Qq | Vdq,Wdq
Opcode
  0x0F73 /6 | 0x660F73 /6 | 0x0FF3 /r | 0x660FF3 /r
CPU
  PX+

    IimPSLLQ:: PROC
        MOV CL,0xF3
        MOV EAX,iiPpgModRMd + 6<<28  ; ModRM /6                                                     ;; >>
        JMP IimPSRLQ.Q:
     ENDP IimPSLLQ::

↑ IimGroupSSE2
  IimGroupSSE2 is a common handler for MMX and SSE2 instructions with format mmx,mmx/mem and xmm,xmm/mem with two-byte opcode 0x0F.
Input
  CL is secondary opcode.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
Tested by
  t3615 t3620 t3625 t3630 t3635 t3640

    IimGroupSSE2:: PROC
         IiEmitOpcode 0x0F,ECX
         IiOpEn RM
         IiModRM /r
         IiDispatchFormat mmx.mmx, mmx.mem, xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
         IiRequire SSE2
         IiEmitPrefix OTOGGLE
    .mmx.mmx:
    .mmx.mem:
         RET
     ENDP IimGroupSSE2::

↑ PUNPCKLBW
  Unpack Low Data
Description
  PUNPCKLBW
Category
  mmx,unpack
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F60 /r | 0x660F60 /r
CPU
  PX+
Tested by
  t3615

    IimPUNPCKLBW:: PROC
        MOV CL,0x60
        JMP IimGroupSSE2
     ENDP IimPUNPCKLBW::

↑ PUNPCKLWD
  Unpack Low Data
Description
  PUNPCKLWD
Category
  mmx,unpack
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F61 /r | 0x660F61 /r
CPU
  PX+
Tested by
  t3615

    IimPUNPCKLWD:: PROC
        MOV CL,0x61
        JMP IimGroupSSE2
     ENDP IimPUNPCKLWD::

↑ PUNPCKLDQ
  Unpack Low Data
Description
  PUNPCKLDQ
Category
  mmx,unpack
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F62 /r | 0x660F62 /r
CPU
  PX+
Tested by
  t3615

    IimPUNPCKLDQ:: PROC
        MOV CL,0x62
        JMP IimGroupSSE2
     ENDP IimPUNPCKLDQ::

↑ PACKSSWB
  Pack with Signed Saturation
Description
  PACKSSWB
Category
  mmx,conver
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F63 /r | 0x660F63 /r
CPU
  PX+
Tested by
  t3615

    IimPACKSSWB:: PROC
        MOV CL,0x63
        JMP IimGroupSSE2
     ENDP IimPACKSSWB::

↑ PCMPGTB
  Compare Packed Signed Integers for Greater Than
Description
  PCMPGTB
Category
  mmx,compar
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F64 /r | 0x660F64 /r
CPU
  PX+
Tested by
  t3615

    IimPCMPGTB:: PROC
        MOV CL,0x64
        JMP IimGroupSSE2
     ENDP IimPCMPGTB::

↑ PCMPGTW
  Compare Packed Signed Integers for Greater Than
Description
  PCMPGTW
Category
  mmx,compar
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F65 /r | 0x660F65 /r
CPU
  PX+
Tested by
  t3615

    IimPCMPGTW:: PROC
        MOV CL,0x65
        JMP IimGroupSSE2
     ENDP IimPCMPGTW::

↑ PCMPGTD
  Compare Packed Signed Integers for Greater Than
Description
  PCMPGTD
Category
  mmx,compar
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0F66 /r | 0x660F66 /r
CPU
  PX+
Tested by
  t3615

    IimPCMPGTD:: PROC
        MOV CL,0x66
        JMP IimGroupSSE2
     ENDP IimPCMPGTD::

↑ PACKUSWB
  Pack with Unsigned Saturation
Description
  PACKUSWB
Category
  mmx,conver
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F67 /r | 0x660F67 /r
CPU
  PX+
Tested by
  t3615

    IimPACKUSWB:: PROC
        MOV CL,0x67
        JMP IimGroupSSE2
     ENDP IimPACKUSWB::

↑ PUNPCKHBW
  Unpack High Data
Description
  PUNPCKHBW
Category
  mmx,unpack
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F68 /r | 0x660F68 /r
CPU
  PX+
Tested by
  t3620

    IimPUNPCKHBW:: PROC
        MOV CL,0x68
        JMP IimGroupSSE2
     ENDP IimPUNPCKHBW::

↑ PUNPCKHWD
  Unpack High Data
Description
  PUNPCKHWD
Category
  mmx,unpack
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F69 /r | 0x660F69 /r
CPU
  PX+
Tested by
  t3620

    IimPUNPCKHWD:: PROC
        MOV CL,0x69
        JMP IimGroupSSE2
     ENDP IimPUNPCKHWD::

↑ PUNPCKHDQ
  Unpack High Data
Description
  PUNPCKHDQ
Category
  mmx,unpack
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F6A /r | 0x660F6A /r
CPU
  PX+
Tested by
  t3620

    IimPUNPCKHDQ:: PROC
        MOV CL,0x6A
        JMP IimGroupSSE2
     ENDP IimPUNPCKHDQ::

↑ PACKSSDW
  Pack with Signed Saturation
Description
  PACKSSDW
Category
  mmx,conver
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F6B /r | 0x660F6B /r
CPU
  PX+
Tested by
  t3620

    IimPACKSSDW:: PROC
        MOV CL,0x6B
        JMP IimGroupSSE2
     ENDP IimPACKSSDW::

↑ PCMPEQB
  Compare Packed Data for Equal
Description
  PCMPEQB
Category
  mmx,compar
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F74 /r | 0x660F74 /r
CPU
  PX+
Tested by
  t3620

    IimPCMPEQB:: PROC
        MOV CL,0x74
        JMP IimGroupSSE2
     ENDP IimPCMPEQB::

↑ PCMPEQW
  Compare Packed Data for Equal
Description
  PCMPEQW
Category
  mmx,compar
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F75 /r | 0x660F75 /r
CPU
  PX+
Tested by
  t3620

    IimPCMPEQW:: PROC
        MOV CL,0x75
        JMP IimGroupSSE2
     ENDP IimPCMPEQW::

↑ PCMPEQD
  Compare Packed Data for Equal
Description
  PCMPEQD
Category
  mmx,compar
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F76 /r | 0x660F76 /r
CPU
  PX+
Tested by
  t3620

    IimPCMPEQD:: PROC
        MOV CL,0x76
        JMP IimGroupSSE2
     ENDP IimPCMPEQD::

↑ PADDQ
  Add Packed Quadword Integers
Description
  PADDQ
Category
  sse2,simdint,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FD4 /r | 0x660FD4 /r
CPU
  PX+
Tested by
  t3620

    IimPADDQ:: PROC
        MOV CL,0xD4
        JMP IimGroupSSE2
     ENDP IimPADDQ::

↑ PMULLW
  Multiply Packed Signed Integers and Store Low Result
Description
  PMULLW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FD5 /r | 0x660FD5 /r
CPU
  PX+
Tested by
  t3625

    IimPMULLW:: PROC
        MOV CL,0xD5
        JMP IimGroupSSE2
     ENDP IimPMULLW::

↑ PSUBUSB
  Subtract Packed Unsigned Integers with Unsigned Saturation
Description
  PSUBUSB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FD8 /r | 0x660FD8 /r
CPU
  PX+
Tested by
  t3625

    IimPSUBUSB:: PROC
        MOV CL,0xD8
        JMP IimGroupSSE2
     ENDP IimPSUBUSB::

↑ PSUBUSW
  Subtract Packed Unsigned Integers with Unsigned Saturation
Description
  PSUBUSW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FD9 /r | 0x660FD9 /r
CPU
  PX+
Tested by
  t3625

    IimPSUBUSW:: PROC
        MOV CL,0xD9
        JMP IimGroupSSE2
     ENDP IimPSUBUSW::

↑ PMINUB
  Minimum of Packed Unsigned Byte Integers
Description
  PMINUB
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FDA /r | 0x660FDA /r
CPU
  P3+
Tested by
  t3625

    IimPMINUB:: PROC
        MOV CL,0xDA
        JMP IimGroupSSE2
     ENDP IimPMINUB::

↑ PAND
  Logical AND
Description
  PAND
Category
  mmx,logical
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0FDB /r | 0x660FDB /r
CPU
  PX+
Tested by
  t3625

    IimPAND:: PROC
        MOV CL,0xDB
        JMP IimGroupSSE2
     ENDP IimPAND::

↑ PADDUSB
  Add Packed Unsigned Integers with Unsigned Saturation
Description
  PADDUSB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FDC /r | 0x660FDC /r
CPU
  PX+
Tested by
  t3625

    IimPADDUSB:: PROC
        MOV CL,0xDC
        JMP IimGroupSSE2
     ENDP IimPADDUSB::

↑ PADDUSW
  Add Packed Unsigned Integers with Unsigned Saturation
Description
  PADDUSW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FDD /r | 0x660FDD /r
CPU
  PX+
Tested by
  t3625

    IimPADDUSW:: PROC
        MOV CL,0xDD
        JMP IimGroupSSE2
     ENDP IimPADDUSW::

↑ PMAXUB
  Maximum of Packed Unsigned Byte Integers
Description
  PMAXUB
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FDE /r | 0x660FDE /r
CPU
  P3+
Tested by
  t3625

    IimPMAXUB:: PROC
        MOV CL,0xDE
        JMP IimGroupSSE2
     ENDP IimPMAXUB::

↑ PANDN
  Logical AND NOT
Description
  PANDN
Category
  mmx,logical
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FDF /r | 0x660FDF /r
CPU
  PX+
Tested by
  t3630

    IimPANDN:: PROC
        MOV CL,0xDF
        JMP IimGroupSSE2
     ENDP IimPANDN::

↑ PAVGB
  Average Packed Integers
Description
  PAVGB
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE0 /r | 0x660FE0 /r
CPU
  P3+
Tested by
  t3630

    IimPAVGB:: PROC
        MOV CL,0xE0
        JMP IimGroupSSE2
     ENDP IimPAVGB::

↑ PAVGW
  Average Packed Integers
Description
  PAVGW
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE3 /r | 0x660FE3 /r
CPU
  P3+
Tested by
  t3630

    IimPAVGW:: PROC
        MOV CL,0xE3
        JMP IimGroupSSE2
     ENDP IimPAVGW::

↑ PMULHUW
  Multiply Packed Unsigned Integers and Store High Result
Description
  PMULHUW
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE4 /r | 0x660FE4 /r
CPU
  P3+
Tested by
  t3630

    IimPMULHUW:: PROC
        MOV CL,0xE4
        JMP IimGroupSSE2
     ENDP IimPMULHUW::

↑ PMULHW
  Multiply Packed Signed Integers and Store High Result
Description
  PMULHW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE5 /r | 0x660FE5 /r
CPU
  PX+
Tested by
  t3630

    IimPMULHW:: PROC
        MOV CL,0xE5
        JMP IimGroupSSE2
     ENDP IimPMULHW::

↑ PSUBSB
  Subtract Packed Signed Integers with Signed Saturation
Description
  PSUBSB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE8 /r | 0x660FE8 /r
CPU
  PX+
Tested by
  t3630

    IimPSUBSB:: PROC
        MOV CL,0xE8
        JMP IimGroupSSE2
     ENDP IimPSUBSB::

↑ PSUBSW
  Subtract Packed Signed Integers with Signed Saturation
Description
  PSUBSW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FE9 /r | 0x660FE9 /r
CPU
  PX+
Tested by
  t3630

    IimPSUBSW:: PROC
        MOV CL,0xE9
        JMP IimGroupSSE2
     ENDP IimPSUBSW::

↑ PMINSW
  Minimum of Packed Signed Word Integers
Description
  PMINSW
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FEA /r | 0x660FEA /r
CPU
  P3+
Tested by
  t3630

    IimPMINSW:: PROC
        MOV CL,0xEA
        JMP IimGroupSSE2
     ENDP IimPMINSW::

↑ POR
  Bitwise Logical OR
Description
  POR
Category
  mmx,logical
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FEB /r | 0x660FEB /r
CPU
  PX+
Tested by
  t3635

    IimPOR:: PROC
        MOV CL,0xEB
        JMP IimGroupSSE2
     ENDP IimPOR::

↑ PADDSB
  Add Packed Signed Integers with Signed Saturation
Description
  PADDSB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FEC /r | 0x660FEC /r
CPU
  PX+
Tested by
  t3635

    IimPADDSB:: PROC
        MOV CL,0xEC
        JMP IimGroupSSE2
     ENDP IimPADDSB::

↑ PADDSW
  Add Packed Signed Integers with Signed Saturation
Description
  PADDSW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FED /r | 0x660FED /r
CPU
  PX+
Tested by
  t3635

    IimPADDSW:: PROC
        MOV CL,0xED
        JMP IimGroupSSE2
     ENDP IimPADDSW::

↑ PMAXSW
  Maximum of Packed Signed Word Integers
Description
  PMAXSW
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FEE /r | 0x660FEE /r
CPU
  P3+
Tested by
  t3635

    IimPMAXSW:: PROC
        MOV CL,0xEE
        JMP IimGroupSSE2
     ENDP IimPMAXSW::

↑ PXOR
  Logical Exclusive OR
Description
  PXOR
Category
  mmx,logical
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FEF /r | 0x660FEF /r
CPU
  PX+
Tested by
  t3635

    IimPXOR:: PROC
        MOV CL,0xEF
        JMP IimGroupSSE2
     ENDP IimPXOR::

↑ PMULUDQ
  Multiply Packed Unsigned DW Integers
Description
  PMULUDQ
Category
  sse2,simdint,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FF4 /r | 0x660FF4 /r
CPU
  P4+
Tested by
  t3635

    IimPMULUDQ:: PROC
        MOV CL,0xF4
        JMP IimGroupSSE2
     ENDP IimPMULUDQ::

↑ PMADDWD
  Multiply and Add Packed Integers
Description
  PMADDWD
Category
  mmx,arith
Operands
  Pq,Qd | Vdq,Wdq
Opcode
  0x0FF5 /r | 0x660FF5 /r
CPU
  PX+
Tested by
  t3635

    IimPMADDWD:: PROC
        MOV CL,0xF5
        JMP IimGroupSSE2
     ENDP IimPMADDWD::

↑ PSADBW
  Compute Sum of Absolute Differences
Description
  PSADBW
Category
  sse1,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FF6 /r | 0x660FF6 /r
CPU
  P3+
Tested by
  t3635

    IimPSADBW:: PROC
        MOV CL,0xF6
        JMP IimGroupSSE2
     ENDP IimPSADBW::

↑ PSUBB
  Subtract Packed Integers
Description
  PSUBB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FF8 /r | 0x660FF8 /r
CPU
  PX+
Tested by
  t3640

    IimPSUBB:: PROC
        MOV CL,0xF8
        JMP IimGroupSSE2
     ENDP IimPSUBB::

↑ PSUBW
  Subtract Packed Integers
Description
  PSUBW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FF9 /r | 0x660FF9 /r
CPU
  PX+
Tested by
  t3640

    IimPSUBW:: PROC
        MOV CL,0xF9
        JMP IimGroupSSE2
     ENDP IimPSUBW::

↑ PSUBD
  Subtract Packed Integers
Description
  PSUBD
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FFA /r | 0x660FFA /r
CPU
  PX+
Tested by
  t3640

    IimPSUBD:: PROC
        MOV CL,0xFA
        JMP IimGroupSSE2
     ENDP IimPSUBD::

↑ PSUBQ
  Subtract Packed Quadword Integers
Description
  PSUBQ
Category
  sse2,simdint,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FFB /r | 0x660FFB /r
CPU
  P4+
Tested by
  t3640

    IimPSUBQ:: PROC
        MOV CL,0xFB
        JMP IimGroupSSE2
     ENDP IimPSUBQ::

↑ PADDB
  Add Packed Integers
Description
  PADDB
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FFC /r | 0x660FFC /r
CPU
  PX+
Tested by
  t3640

    IimPADDB:: PROC
        MOV CL,0xFC
        JMP IimGroupSSE2
     ENDP IimPADDB::

↑ PADDW
  Add Packed Integers
Description
  PADDW
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FFD /r | 0x660FFD /r
CPU
  PX+
Tested by
  t3640

    IimPADDW:: PROC
        MOV CL,0xFD
        JMP IimGroupSSE2
     ENDP IimPADDW::

↑ PADDD
  Add Packed Integers
Description
  PADDD
Category
  mmx,arith
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0FFE /r | 0x660FFE /r
CPU
  PX+
Tested by
  t3640

    IimPADDD:: PROC
        MOV CL,0xFE
        JMP IimGroupSSE2
     ENDP IimPADDD::

↑ EMMS
  Empty MMX Technology State
Description
  EMMS
Category
  mmx,x87fpu,control
Opcode
  0x0F77
CPU
  PX+
Tested by
  t3645

    IimEMMS:: PROC
        IiRequire MMX,FPU
        IiEmitOpcode 0x0F,0x77
        IiDispatchFormat none
    .none:RET
     ENDP IimEMMS::

↑ MASKMOVQ
  Store Selected Bytes of Quadword
Description
  MASKMOVQ
Category
  sse1,cachect
Operands
  BDq,Pq,Nq
Opcode
  0x0FF7 /r
CPU
  P3+
Documented
  D40
Tested by
  t3645

    IimMASKMOVQ:: PROC
        IiEmitOpcode 0x0F,0xF7
        IiDispatchFormat mmx.mmx, mem.mmx.mmx
    .mem.mmx.mmx:
        IiStringDestination Operand1, AllowSeg=YES
        IiSwap Operand1,Operand2 ; Get rid of Operand1.
        IiSwap Operand2,Operand3
    .mmx.mmx:
        IiOpEn RM
        IiModRM /r
        RET
     ENDP IimMASKMOVQ::

↑ MOVNTQ
  Store of Quadword Using Non-Temporal Hint
Description
  MOVNTQ
Operands
  m64,mm
Opcode
  0F E7 /r
Tested by
  t3645

    IimMOVNTQ:: PROC
        IiRequire 686,SSE1
        IiEmitOpcode 0x0F,0xE7
        IiOpEn MR
        IiModRM /r
        IiDispatchFormat mem.mmx
    .mem.mmx:RET
     ENDP IimMOVNTQ::

↑ PINSRW
  Insert Word
Description
  PINSRW
Category
  sse1,simdint
Operands
  Pq,Rdqp,Ib | Pq,Mw,Ib | Vdq,Rdqp,Ib | Vdq,Mw,Ib
Opcode
  0x0FC4 /r | 0x0FC4 /r | 0x660FC4 /r | 0x660FC4 /r
CPU
  P3+
Tested by
  t3645 t3730

    IimPINSRW:: PROC
        IiEmitOpcode 0x0F,0xC4
        IiAllowModifier IMM,DATA
        IiEncoding DATA=WORD
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3,BYTE
        IiDispatchFormat xmm.r16.imm, xmm.r32.imm, xmm.r64.imm, xmm.mem.imm, \
                         mmx.r16.imm, mmx.r32.imm, mmx.r64.imm, mmx.mem.imm
    .xmm.r16.imm:
    .xmm.r32.imm:
    .xmm.r64.imm:
    .xmm.mem.imm:
        IiRequire SSE2
        IiEmitPrefix OTOGGLE
    .mmx.r16.imm:
    .mmx.r32.imm:
    .mmx.r64.imm:
    .mmx.mem.imm:
        RET
     ENDP IimPINSRW::

↑ PMOVMSKB
  Move Byte Mask
Description
  PMOVMSKB
Category
  sse1,simdint
Operands
  Gdqp,Nq | Gdqp,Udq
Opcode
  0x0FD7 /r | 0x660FD7 /r
CPU
  P3+
Tested by
  t3645

    IimPMOVMSKB:: PROC
        IiRequire 686,SSE
        IiEmitOpcode 0x0F,0xD7
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat r32.mmx, r32.xmm
    .r32.xmm:
        IiEmitPrefix OTOGGLE
    .r32.mmx:
        RET
     ENDP IimPMOVMSKB::

↑ PSHUFW
  Shuffle Packed Words
Description
  PSHUFW
Category
  sse1,simdint
Operands
  Pq,Qq,Ib
Opcode
  0x0F70 /r
CPU
  P3+
Tested by
  t3645

    IimPSHUFW:: PROC
        IiRequire 686,SSE
        IiAllowModifier IMM
        IiEmitOpcode 0x0F,0x70
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3,BYTE
        IiDispatchFormat mmx.mmx.imm, mmx.mem.imm
    .mmx.mem.imm:
    .mmx.mmx.imm:
        RET
     ENDP IimPSHUFW::

↑ PALIGNR
  Packed Align Right
Description
  PALIGNR
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3A0F /r | 0x660F3A0F /r
CPU
  C2+
Tested by
  t3600

    IimPALIGNR:: PROC
        IiRequire SSSE3
        IiAllowModifier IMM
        IiEmitOpcode 0x0F,0x3A,0x0F
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3,BYTE
        IiDispatchFormat mmx.mmx.imm, mmx.mem.imm, xmm.xmm.imm, xmm.mem.imm
    .xmm.xmm.imm:
    .xmm.mem.imm:
        IiEmitPrefix OTOGGLE
    .mmx.mmx.imm:
    .mmx.mem.imm:
        RET
     ENDP IimPALIGNR::

↑ IimGroupSSE3
  IimGroupSSE3 is a common handler for MMX and SSE instructions with format mmx,mmx/mem and xmm,xmm/mem with three-byte opcode 0x0F,0x38,CL.
Input
  CL is tertiary opcode.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
Tested by
  t3650 t3655

    IimGroupSSE3:: PROC
         IiRequire SSSE3
         IiEmitOpcode 0x0F,0x38,ECX
         IiOpEn RM
         IiModRM /r
         IiDispatchFormat mmx.mmx, mmx.mem, xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
         IiEmitPrefix OTOGGLE
    .mmx.mmx:
    .mmx.mem:
         RET
     ENDP IimGroupSSE3::

↑ PSHUFB
  Packed Shuffle Bytes
Description
  PSHUFB
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3800 /r | 0x660F3800 /r
CPU
  C2+
Tested by
  t3650

    IimPSHUFB:: PROC
        MOV CL,0x00
        JMP IimGroupSSE3:
     ENDP IimPSHUFB::

↑ PHADDW
  Packed Horizontal Add
Description
  PHADDW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3801 /r | 0x660F3801 /r
CPU
  C2+
Tested by
  t3650

    IimPHADDW:: PROC
        MOV CL,0x01
        JMP IimGroupSSE3:
     ENDP IimPHADDW::

↑ PHADDD
  Packed Horizontal Add
Description
  PHADDD
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3802 /r | 0x660F3802 /r
CPU
  C2+
Tested by
  t3650

    IimPHADDD:: PROC
        MOV CL,0x02
        JMP IimGroupSSE3:
     ENDP IimPHADDD::

↑ PHADDSW
  Packed Horizontal Add and Saturate
Description
  PHADDSW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3803 /r | 0x660F3803 /r
CPU
  C2+
Tested by
  t3650

    IimPHADDSW:: PROC
        MOV CL,0x03
        JMP IimGroupSSE3:
     ENDP IimPHADDSW::

↑ PMADDUBSW
  Multiply and Add Packed Signed and Unsigned Bytes
Description
  PMADDUBSW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3804 /r | 0x660F3804 /r
CPU
  C2+
Tested by
  t3650

    IimPMADDUBSW:: PROC
        MOV CL,0x04
        JMP IimGroupSSE3:
     ENDP IimPMADDUBSW::

↑ PHSUBW
  Packed Horizontal Subtract
Description
  PHSUBW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3805 /r | 0x660F3805 /r
CPU
  C2+
Tested by
  t3650

    IimPHSUBW:: PROC
        MOV CL,0x05
        JMP IimGroupSSE3:
     ENDP IimPHSUBW::

↑ PHSUBD
  Packed Horizontal Subtract
Description
  PHSUBD
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3806 /r | 0x660F3806 /r
CPU
  C2+
Tested by
  t3650

    IimPHSUBD:: PROC
        MOV CL,0x06
        JMP IimGroupSSE3:
     ENDP IimPHSUBD::

↑ PHSUBSW
  Packed Horizontal Subtract and Saturate
Description
  PHSUBSW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3807 /r | 0x660F3807 /r
CPU
  C2+
Tested by
  t3650

    IimPHSUBSW:: PROC
        MOV CL,0x07
        JMP IimGroupSSE3:
     ENDP IimPHSUBSW::

↑ PSIGNB
  Packed SIGN
Description
  PSIGNB
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3808 /r | 0x660F3808 /r
CPU
  C2+
Tested by
  t3655

    IimPSIGNB:: PROC
        MOV CL,0x08
        JMP IimGroupSSE3:
     ENDP IimPSIGNB::

↑ PSIGNW
  Packed SIGN
Description
  PSIGNW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3809 /r | 0x660F3809 /r
CPU
  C2+
Tested by
  t3655

    IimPSIGNW:: PROC
        MOV CL,0x09
        JMP IimGroupSSE3:
     ENDP IimPSIGNW::

↑ PSIGND
  Packed SIGN
Description
  PSIGND
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F380A /r | 0x660F380A /r
CPU
  C2+
Tested by
  t3655

    IimPSIGND:: PROC
        MOV CL,0x0A
        JMP IimGroupSSE3:
     ENDP IimPSIGND::

↑ PMULHRSW
  Packed Multiply High with Round and Scale
Description
  PMULHRSW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F380B /r | 0x660F380B /r
CPU
  C2+
Tested by
  t3655

    IimPMULHRSW:: PROC
        MOV CL,0x0B
        JMP IimGroupSSE3:
     ENDP IimPMULHRSW::

↑ PABSB
  Packed Absolute Value
Description
  PABSB
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F381C /r | 0x660F381C /r
CPU
  C2+
Tested by
  t3655

    IimPABSB:: PROC
        MOV CL,0x1C
        JMP IimGroupSSE3:
     ENDP IimPABSB::

↑ PABSW
  Packed Absolute Value
Description
  PABSW
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F381D /r | 0x660F381D /r
CPU
  C2+
Tested by
  t3655

    IimPABSW:: PROC
        MOV CL,0x1D
        JMP IimGroupSSE3:
     ENDP IimPABSW::

↑ PABSD
  Packed Absolute Value
Description
  PABSD
Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F381E /r | 0x660F381E /r
CPU
  C2+
Tested by
  t3655

    IimPABSD:: PROC
        MOV CL,0x1E
        JMP IimGroupSSE3:
     ENDP IimPABSD::

↑ CVTPI2PD
  Convert Packed DW Integers to Double-FP Values
Description
  CVTPI2PD
Category
  sse2,pcksclr,conver
Operands
  Vpd,Qpi
Opcode
  0x660F2A /r
CPU
  P4+
Tested by
  t3660

    IimCVTPI2PD:: PROC
        IiRequire 686,SSE2
        IiEmitPrefix OTOGGLE
        IiEmitOpcode 0x0F,0x2A
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat xmm.mmx, xmm.mem
    .xmm.mem:
    .xmm.mmx:
        RET
     ENDP IimCVTPI2PD::

↑ CVTTPD2PI
  Convert with Trunc. Packed Double-FP Values to DW Integers
Description
  CVTTPD2PI
Category
  sse2,pcksclr,conver
Operands
  Ppi,Wpd
Opcode
  0x660F2C /r
CPU
  P4+
Tested by
  t3660

    IimCVTTPD2PI:: PROC
        IiRequire 686,SSE2
        IiEmitPrefix OTOGGLE
        IiEmitOpcode 0x0F,0x2C
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat mmx.xmm, mmx.mem
    .mmx.mem:
    .mmx.xmm:
        RET
     ENDP IimCVTTPD2PI::

↑ CVTPD2PI
  Convert Packed Double-FP Values to DW Integers
Description
  CVTPD2PI
Category
  sse2,pcksclr,conver
Operands
  Ppi,Wpd
Opcode
  0x660F2D /r
CPU
  P4+
Tested by
  t3660

    IimCVTPD2PI:: PROC
        IiRequire 686,SSE2
        IiEmitPrefix OTOGGLE
        IiEmitOpcode 0x0F,0x2D
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat mmx.xmm, mmx.mem
    .mmx.mem:
    .mmx.xmm:
        RET
     ENDP IimCVTPD2PI::

↑ CVTPS2PI
  Convert Packed Single-FP Values to DW Integers
Description
  CVTPS2PI
Category
  sse1,conver
Operands
  Ppi,Wpsq
Opcode
  0x0F2D /r
CPU
  P3+
Tested by
  t3660

    IimCVTPS2PI:: PROC
        IiRequire 686,SSE
        IiEmitOpcode 0x0F,0x2D
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat mmx.xmm, mmx.mem
    .mmx.mem:
    .mmx.xmm:
        RET
     ENDP IimCVTPS2PI::

↑ CVTTPS2PI
  Convert with Trunc. Packed Single-FP Values to DW Integers
Description
  CVTTPS2PI
Category
  sse1,conver
Operands
  Ppi,Wpsq
Opcode
  0x0F2C /r
CPU
  P3+
Tested by
  t3660

    IimCVTTPS2PI:: PROC
        IiRequire 686,SSE
        IiEmitOpcode 0x0F,0x2C
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat mmx.xmm, mmx.mem
    .mmx.mem:
    .mmx.xmm:
        RET
     ENDP IimCVTTPS2PI::

↑ CVTPI2PS
  Convert Packed DW Integers to Single-FP Values
Description
  CVTPI2PS
Category
  sse1,conver
Operands
  Vps,Qpi
Opcode
  0x0F2A /r
CPU
  P3+
Tested by
  t3660

    IimCVTPI2PS:: PROC
        IiEmitOpcode 0x0F,0x2A
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat xmm.mmx,xmm.mem
    .xmm.mmx:
    .xmm.mem:
        RET
     ENDP IimCVTPI2PS::

↑ MOVDQ2Q
  Move Quadword from XMM to MMX Technology Register
Description
  MOVDQ2Q
Category
  sse2,simdint,datamov
Operands
  Pq,Uq
Opcode
  0xF20FD6 /r
CPU
  P4+
Tested by
  t3660

    IimMOVDQ2Q:: PROC
        IiRequire 686,SSE2
        IiEmitPrefix REPNE
        IiEmitOpcode 0x0F,0xD6
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat mmx.xmm
    .mmx.xmm:RET
     ENDP IimMOVDQ2Q::

↑ MOVQ2DQ
  Move Quadword from MMX Technology to XMM Register
Description
  MOVQ2DQ
Category
  sse2,simdint,datamov
Operands
  Vdq,Nq
Opcode
  0xF30FD6 /r
CPU
  P4+
Tested by
  t3660

    IimMOVQ2DQ:: PROC
        IiRequire 686,SSE2
        IiEmitPrefix REPE
        IiEmitOpcode 0x0F,0xD6
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat xmm.mmx
    .xmm.mmx:RET
     ENDP IimMOVQ2DQ::

↑ PEXTRW
  Extract Word
Description
  PEXTRW
Category
  sse41,simdint,datamov
Operands
  Mw,Vdq,Ib | Rdqp,Vdq,Ib | Gdqp,Nq,Ib | Gdqp,Udq,Ib
Opcode
  0x660F3A15 /r | 0x660F3A15 /r | 0x0FC5 /r | 0x660FC5 /r
CPU
  C2++
Documented
  D43
Tested by
  t3695

    IimPEXTRW:: PROC
        IiAllowModifier IMM,DATA,CODE
        IiEmitOpcode 0x0F
        IiModRM /r
        IiEmitImm Operand3,BYTE
        IiDispatchFormat mem.xmm.imm, r32.xmm.imm, r32.mmx.imm, \
                         mem.xmm.imm, r64.xmm.imm, r64.mmx.imm
    .mem.xmm.imm:
        IiEncoding CODE=LONG,DATA=WORD
        IiRequire SSE4.1
        IiEmitPrefix OTOGGLE
        IiEmitOpcode 0x3A,0x15
        IiOpEn MR
        RET
    .r64.xmm.imm:
        IiEmitPrefix REX.W
    .r32.xmm.imm:
        IiDispatchCode LONG=.mem.xmm.imm:
        IiEmitPrefix OTOGGLE
        JMPS .r32.mmx.imm:
    .r64.mmx.imm:
        IiEmitPrefix REX.W
    .r32.mmx.imm:
        IiEncoding CODE=SHORT,DATA=WORD
        IiEmitOpcode 0xC5
        IiOpEn RM
        RET
     ENDP IimPEXTRW::

      ENDPROGRAM iim

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