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# Test t5170: AVX VSIB addressing mode

Description
  Addressing mode with ModRM+SIB byte where indexregister is SSE vector. Used in gather/scatter instruction family.
Tested procedures
  IiModRM ExpEval IiFlush

Source & expected listing t5170.htm.lst
  `| |EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=34,DUMPALL=OFF,CPU=X64,SIMD=AVX512,EVEX=ON | |t5170 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF |[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE |00000000: | ; VEX encoded VSIB instruction with legal register combinations in 64bit mode: |00000000:C4E261900C13 | VPGATHERDD XMM1,[RBX+1*XMM2],XMM3 |00000006:C4E261900C53 | VPGATHERDD XMM1,[RBX+2*XMM2],XMM3 |0000000C:C4E261900C93 | VPGATHERDD XMM1,[RBX+4*XMM2],XMM3 |00000012:C4E261900CD3 | VPGATHERDD XMM1,[RBX+8*XMM2],XMM3 |00000018:C4E261904C1500 | VPGATHERDD XMM1,[RBP+1*XMM2],XMM3 |0000001F:C4E261904C5500 | VPGATHERDD XMM1,[RBP+2*XMM2],XMM3 |00000026:C4E261904C9500 | VPGATHERDD XMM1,[RBP+4*XMM2],XMM3 |0000002D:C4E261904CD500 | VPGATHERDD XMM1,[RBP+8*XMM2],XMM3 |00000034:C4E261900C1500000000 | VPGATHERDD XMM1,[1*XMM2],XMM3 |0000003E:C4E261900C5500000000 | VPGATHERDD XMM1,[2*XMM2],XMM3 |00000048:C4E261900C9500000000 | VPGATHERDD XMM1,[4*XMM2],XMM3 |00000052:C4E261900CD500000000 | VPGATHERDD XMM1,[8*XMM2],XMM3 |0000005C:C46261900CD500000000 | VPGATHERDD XMM9,[8*XMM2],XMM3 |00000066:C4A261900CD500000000 | VPGATHERDD XMM1,[8*XMM10],XMM3 |00000070:C4E221900CD500000000 | VPGATHERDD XMM1,[8*XMM2],XMM11 |0000007A:C42221900CD500000000 | VPGATHERDD XMM9,[8*XMM10],XMM11 |00000084:C4E261904C1500 | VPGATHERDD XMM1,[RBP+XMM2],XMM3 |0000008B:C4E261904C1540 | VPGATHERDD XMM1,[RBP+XMM2+40h],XMM3 |00000092:C4E261908C1500400000 | VPGATHERDD XMM1,[RBP+XMM2+4000h],XMM3 |0000009C:C4E261900C14 | VPGATHERDD XMM1,[RSP+XMM2],XMM3 |000000A2:C4E261904C1440 | VPGATHERDD XMM1,[RSP+XMM2+40h],XMM3 |000000A9:C4E261908C1400400000 | VPGATHERDD XMM1,[RSP+XMM2+4000h],XMM3 |000000B3:C4C261900C14 | VPGATHERDD XMM1,[R12+XMM2],XMM3 |000000B9:C4C261904C1440 | VPGATHERDD XMM1,[R12+XMM2+40h],XMM3 |000000C0:C4C261908C1400400000 | VPGATHERDD XMM1,[R12+XMM2+4000h],XMM3 |000000CA:C4C261904C1500 | VPGATHERDD XMM1,[R13+XMM2],XMM3 |000000D1:C4C261904C1540 | VPGATHERDD XMM1,[R13+XMM2+40h],XMM3 |000000D8:C4C261908C1500400000 | VPGATHERDD XMM1,[R13+XMM2+4000h],XMM3 |000000E2:67C4E261904C1500 | VPGATHERDD XMM1,[EBP+XMM2],XMM3 |000000EA:67C4C261904C1500 | VPGATHERDD XMM1,[R13D+XMM2],XMM3 |000000F2: | ; EVEX encoded VSIB instruction with legal register combinations in 64bit mode: |000000F2:62F27D0B900C13 | VPGATHERDD XMM1,[RBX+1*XMM2],MASK=K3 |000000F9:62F27D0B900C53 | VPGATHERDD XMM1,[RBX+2*XMM2],MASK=K3 |00000100:62F27D0B900C93 | VPGATHERDD XMM1,[RBX+4*XMM2],MASK=K3 |00000107:62F27D0B900CD3 | VPGATHERDD XMM1,[RBX+8*XMM2],MASK=K3 |0000010E:62F27D0B904C1500<2 | VPGATHERDD XMM1,[RBP+1*XMM2],MASK=K3 |00000116:62F27D0B904C5500<2 | VPGATHERDD XMM1,[RBP+2*XMM2],MASK=K3 |0000011E:62F27D0B904C9500<2 | VPGATHERDD XMM1,[RBP+4*XMM2],MASK=K3 |00000126:62F27D0B904CD500<2 | VPGATHERDD XMM1,[RBP+8*XMM2],MASK=K3 |0000012E:62F27D0B900C1500000000 | VPGATHERDD XMM1,[1*XMM2],MASK=K3 |00000139:62F27D0B900C5500000000 | VPGATHERDD XMM1,[2*XMM2],MASK=K3 |00000144:62F27D0B900C9500000000 | VPGATHERDD XMM1,[4*XMM2],MASK=K3 |0000014F:62F27D0B900CD500000000 | VPGATHERDD XMM1,[8*XMM2],MASK=K3 |0000015A:62727D0B900CD500000000 | VPGATHERDD XMM9,[8*XMM2],MASK=K3 |00000165:62B27D0B900CD500000000 | VPGATHERDD XMM1,[8*XMM10],MASK=K3 |00000170:62327D0B900CD500000000 | VPGATHERDD XMM9,[8*XMM10],MASK=K3 |0000017B:62E27D0B900CD500000000 | VPGATHERDD XMM17,[8*XMM2],MASK=K3 |00000186:62F27D03900CD500000000 | VPGATHERDD XMM1,[8*XMM18],MASK=K3 |00000191:62E27D03900CD500000000 | VPGATHERDD XMM17,[8*XMM18],MASK=K3 |0000019C:62627D0B900CD500000000 | VPGATHERDD XMM25,[8*XMM2],MASK=K3 |000001A7:62B27D03900CD500000000 | VPGATHERDD XMM1,[8*XMM26],MASK=K3 |000001B2:62227D03900CD500000000 | VPGATHERDD XMM25,[8*XMM26],MASK=K3 |000001BD:62F27D0B904C1500<2 | VPGATHERDD XMM1,[RBP+XMM2],MASK=K3 |000001C5:62F27D0B904C1510<2 | VPGATHERDD XMM1,[RBP+XMM2+40h],MASK=K3 |000001CD:62F27D0B908C1500400000 | VPGATHERDD XMM1,[RBP+XMM2+4000h],MASK=K3 |000001D8:62F27D0B900C14 | VPGATHERDD XMM1,[RSP+XMM2],MASK=K3 |000001DF:62F27D0B904C1410<2 | VPGATHERDD XMM1,[RSP+XMM2+40h],MASK=K3 |000001E7:62F27D0B908C1400400000 | VPGATHERDD XMM1,[RSP+XMM2+4000h],MASK=K3 |000001F2:62D27D0B900C14 | VPGATHERDD XMM1,[R12+XMM2],MASK=K3 |000001F9:62D27D0B904C1410<2 | VPGATHERDD XMM1,[R12+XMM2+40h],MASK=K3 |00000201:62D27D0B908C1400400000 | VPGATHERDD XMM1,[R12+XMM2+4000h],MASK=K3 |0000020C:62D27D0B904C1500<2 | VPGATHERDD XMM1,[R13+XMM2],MASK=K3 |00000214:62D27D0B904C1510<2 | VPGATHERDD XMM1,[R13+XMM2+40h],MASK=K3 |0000021C:62D27D0B908C1500400000 | VPGATHERDD XMM1,[R13+XMM2+4000h],MASK=K3 |00000227:6762B27D03904C1500<2 | VPGATHERDD XMM1,[EBP+XMM26],MASK=K3 |00000230:6762927D03904C1500<2 | VPGATHERDD XMM1,[R13D+XMM26],MASK=K3,ZEROING=DISABLED |00000239: |; VEX encoded VSIB instruction with legal register combinations in 32bit mode: |[Mode32] |[Mode32] SEGMENT WIDTH=32,PURPOSE=CODE |00000000:C4E261900C13 | VPGATHERDD XMM1,[EBX+1*XMM2],XMM3 |00000006:C4E261900C53 | VPGATHERDD XMM1,[EBX+2*XMM2],XMM3 |0000000C:C4E261900C93 | VPGATHERDD XMM1,[EBX+4*XMM2],XMM3 |00000012:C4E261900CD3 | VPGATHERDD XMM1,[EBX+8*XMM2],XMM3 |00000018:C4E261904C1500 | VPGATHERDD XMM1,[EBP+1*XMM2],XMM3 |0000001F:C4E261904C5500 | VPGATHERDD XMM1,[EBP+2*XMM2],XMM3 |00000026:C4E261904C9500 | VPGATHERDD XMM1,[EBP+4*XMM2],XMM3 |0000002D:C4E261904CD500 | VPGATHERDD XMM1,[EBP+8*XMM2],XMM3 |00000034:C4E261900C1500000000 | VPGATHERDD XMM1,[1*XMM2],XMM3 |0000003E:C4E261900C5500000000 | VPGATHERDD XMM1,[2*XMM2],XMM3 |00000048:C4E261900C9500000000 | VPGATHERDD XMM1,[4*XMM2],XMM3 |00000052:C4E261900CD500000000 | VPGATHERDD XMM1,[8*XMM2],XMM3 |0000005C:C4E261904C1500 | VPGATHERDD XMM1,[EBP+XMM2],XMM3 |00000063:C4E261904C1540 | VPGATHERDD XMM1,[EBP+XMM2+40h],XMM3 |0000006A:C4E261908C1500400000 | VPGATHERDD XMM1,[EBP+XMM2+4000h],XMM3 |00000074:C4E261900C14 | VPGATHERDD XMM1,[ESP+XMM2],XMM3 |0000007A:C4E261904C1440 | VPGATHERDD XMM1,[ESP+XMM2+40h],XMM3 |00000081:C4E261908C1400400000 | VPGATHERDD XMM1,[ESP+XMM2+4000h],XMM3 |0000008B:C4E261900C13 | VPGATHERDD XMM1,[EBX+XMM2],XMM3 |00000091: | ; EVEX encoded VSIB instruction with legal register combinations in 32bit mode: |00000091:62F27D0B900C13 | VPGATHERDD XMM1,[EBX+1*XMM2],MASK=K3 |00000098:62F27D0B900C53 | VPGATHERDD XMM1,[EBX+2*XMM2],MASK=K3 |0000009F:62F27D0B900C93 | VPGATHERDD XMM1,[EBX+4*XMM2],MASK=K3 |000000A6:62F27D0B900CD3 | VPGATHERDD XMM1,[EBX+8*XMM2],MASK=K3 |000000AD:62F27D0B904C1500<2 | VPGATHERDD XMM1,[EBP+1*XMM2],MASK=K3 |000000B5:62F27D0B904C5500<2 | VPGATHERDD XMM1,[EBP+2*XMM2],MASK=K3 |000000BD:62F27D0B904C9500<2 | VPGATHERDD XMM1,[EBP+4*XMM2],MASK=K3 |000000C5:62F27D0B904CD500<2 | VPGATHERDD XMM1,[EBP+8*XMM2],MASK=K3 |000000CD:62F27D0B900C1500000000 | VPGATHERDD XMM1,[1*XMM2],MASK=K3 |000000D8:62F27D0B900C5500000000 | VPGATHERDD XMM1,[2*XMM2],MASK=K3 |000000E3:62F27D0B900C9500000000 | VPGATHERDD XMM1,[4*XMM2],MASK=K3 |000000EE:62F27D0B900CD500000000 | VPGATHERDD XMM1,[8*XMM2],MASK=K3 |000000F9:2662F27D0B900C13 | VPGATHERDD XMM1,[ES:EBX+XMM2],MASK=K3,ZEROING=DISABLED |00000101: | ; Intentionally incorrect VSIB operands: |00000101: | VPGATHERDD XMM1,[EBX+0*XMM2],XMM3 ; XMM index missing. E6285 expected. |### E6285 This instruction requires vector indexregister XMM. |00000101: | VPGATHERDD XMM1,[EBP+40h],MASK=K2 ; XMM index missing. E6285 expected. |### E6285 This instruction requires vector indexregister XMM. |00000101: | VPGATHERDD XMM1,[XMM2+XMM3],XMM4 ; Two VSIB indexes. E6274 expected. |### E6274 Unexpected XMM3, only one indexregister is allowed in expression "[XMM2+XMM3]". |00000101: | VPGATHERDD XMM1,[XMM2+4*EDI],MASK=K3 ; Two indexes. E6274 expected. |### E6274 Unexpected XMM2, only one indexregister is allowed in expression "[XMM2+4*EDI]". |00000101: | VPGATHERDD XMM1,[YMM2],XMM3 ; Unexpected VSIB index size. E6285 expected. |### E6285 This instruction requires vector indexregister XMM. |00000101:C4E271900C13 | VPGATHERDD XMM1,[EBX+XMM2],XMM1 ; Destination identical with mask. W3315 expected. |## W3315 Destination, vector index register and mask register should be distinct. |00000107:C4E261900C0B | VPGATHERDD XMM1,[EBX+XMM1],XMM3 ; Destination identical with index. W3315 expected. |## W3315 Destination, vector index register and mask register should be distinct. |0000010D:C4E269900C13 | VPGATHERDD XMM1,[EBX+XMM2],XMM2 ; Index identical with mask. W3315 expected. |## W3315 Destination, vector index register and mask register should be distinct. |00000113:62F27D0B900C0B | VPGATHERDD XMM1,[EBX+XMM1],MASK=K3 ; Destination identical with index. W3315 expected. |## W3315 Destination, vector index register and mask register should be distinct. |0000011A:62F27D08900C13 | VPGATHERDD XMM1,[EBX+XMM2] ; Omitted mask. W3312 expected. |## W3312 No mask specified, this instruction requires MASK=K1..K7. |00000121:62F27D08900C13 | VPGATHERDD XMM1,[EBX+XMM2],MASK=K0 ; Mask K0. W3312 expected. |## W3312 No mask specified, this instruction requires MASK=K1..K7. |00000128:62F27D8B900C13 | VPGATHERDD XMM1,[EBX+XMM2],MASK=K3,ZEROING=ON ; Zeroing is illegal with VSIB. W3313 expected. |## W3313 Zeroing is not allowed in this instruction. |0000012F:67C4E261900C1500000000 | ATOGGLE VPGATHERDD XMM1,[XMM2],XMM3 ; VSIB is illegal in 16bit addressing mode. W2371 expected. |## W2371 Prefix ATOGGLE: is not expected in this instruction. |[Mode16] |[Mode16] SEGMENT WIDTH=16,PURPOSE=CODE |0000:67C4E261900C1500000000 | VPGATHERDD XMM1,[XMM2],XMM3 ; VSIB toggles to 32bit addressing mode in 16bit segment. |000B:C4E261900F | VPGATHERDD XMM1,[BX+XMM2],XMM3 ; VSIB is illegal in 16bit addressing mode. E6744 expected. |### E6744 This VSIB instruction cannot be used in 16bit addressing mode. |0010:62F27D0B900F | VPGATHERDD XMM1,[BX+XMM2],MASK=K3 ; VSIB is illegal in 16bit addressing mode. E6744 expected. |### E6744 This VSIB instruction cannot be used in 16bit addressing mode. | |ENDPROGRAM t5170`

Expected messages t5170.out
  `I0180 Assembling source file "t5170.htm". I0270 Assembling source "t5170". I0310 Assembling source pass 1. I0330 Assembling source pass 2 - final. I0470 Assembling program "t5170". "t5170.htm"{58} I0510 Assembling program pass 1. "t5170.htm"{58} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{163} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{165} E6274 Unexpected XMM3, only one indexregister is allowed in expression "[XMM2+XMM3]". "t5170.htm"{167} E6274 Unexpected XMM2, only one indexregister is allowed in expression "[XMM2+4*EDI]". "t5170.htm"{169} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{171} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{173} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{175} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{177} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{179} W3312 No mask specified, this instruction requires MASK=K1..K7. "t5170.htm"{181} W3312 No mask specified, this instruction requires MASK=K1..K7. "t5170.htm"{183} W3313 Zeroing is not allowed in this instruction. "t5170.htm"{185} W2371 Prefix ATOGGLE: is not expected in this instruction. "t5170.htm"{187} E6744 This VSIB instruction cannot be used in 16bit addressing mode. "t5170.htm"{191} E6744 This VSIB instruction cannot be used in 16bit addressing mode. "t5170.htm"{193} I0530 Assembling program pass 2 - final. "t5170.htm"{58} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{163} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{165} E6274 Unexpected XMM3, only one indexregister is allowed in expression "[XMM2+XMM3]". "t5170.htm"{167} E6274 Unexpected XMM2, only one indexregister is allowed in expression "[XMM2+4*EDI]". "t5170.htm"{169} E6285 This instruction requires vector indexregister XMM. "t5170.htm"{171} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{173} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{175} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{177} W3315 Destination, vector index register and mask register should be distinct. "t5170.htm"{179} W3312 No mask specified, this instruction requires MASK=K1..K7. "t5170.htm"{181} W3312 No mask specified, this instruction requires MASK=K1..K7. "t5170.htm"{183} W3313 Zeroing is not allowed in this instruction. "t5170.htm"{185} W2371 Prefix ATOGGLE: is not expected in this instruction. "t5170.htm"{187} E6744 This VSIB instruction cannot be used in 16bit addressing mode. "t5170.htm"{191} E6744 This VSIB instruction cannot be used in 16bit addressing mode. "t5170.htm"{193} I0660 16bit TINY BIN file "t5170.bin" created, size=918. "t5170.htm"{195} I0650 Program "t5170" assembled in 2 passes with errorlevel 6. "t5170.htm"{195} I0750 Source "t5170" (243 lines) assembled in 2 passes with errorlevel 6. I0860 Listing file "t5170.htm.lst" created, size=10946. I0990 EuroAssembler terminated with errorlevel 6.`

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