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# iia.htm
Enumerations
IiaList
Instruction handlers
ANDN MOVBE VAESDEC VAESDECLAST VAESENC VAESENCLAST VAESIMC VAESKEYGENASSIST VFMADDPD VFMADDPS VFMADDSD VFMADDSS VFMADDSUBPD VFMADDSUBPS VFMSUBADDPD VFMSUBADDPS VFMSUBPD VFMSUBPS VFMSUBSD VFMSUBSS VFNMADDPD VFNMADDPS VFNMADDSD VFNMADDSS VFNMSUBPD VFNMSUBPS VFNMSUBSD VFNMSUBSS VPCMPESTRI VPCMPESTRM VPCMPISTRI VPCMPISTRM VPERMILMO2PD VPERMILMO2PS VPERMILMV2PD VPERMILMO2PS VPERMILTD2PD VPERMILTD2PS VPHMINPOSUW VPSIGNB VPSIGND VPSIGNW VPTEST VTESTPD VTESTPS VZEROALL VZEROUPPER

↑ IiaHandlers
  assemble AMD-specific instruction in legacy or VEX encoding.
  For XOP-encoded instructions see iix.htm.
  For 3DNow! instructions see iid.htm.
See also
  IiHandlers, [AMDVol3] [AMDVol6].

    iia PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
        INCLUDEHEAD euroasm.htm, \  Interface (structures, symbols and macros) of other modules used in this source.
                    ea.htm,eaopt.htm,exp.htm,ii.htm,msg.htm,pgm.htm,pgmopt.htm,sss.htm,stm.htm,sym.htm

    iia HEAD ; Start of module interface.

↑ %IiaList
  enumerates machine instructions of this family which €ASM can assemble.
  Each instruction declared in `%IiaList` requires the corresponding handler in this file.
See also
  DictLookupIi

    %IiaList %SET \
    MOVBE, \
    ANDN, \
    VAESENC, \
    VAESENCLAST, \
    VAESDEC, \
    VAESDECLAST, \
    VAESIMC, \
    VAESKEYGENASSIST, \
    VPCMPESTRI, \
    VPCMPESTRM, \
    VPCMPISTRI, \
    VPCMPISTRM, \
    VPSIGNB, \
    VPSIGNW, \
    VPSIGND, \
    VPTEST, \
    VTESTPS, \
    VTESTPD, \
    VPHMINPOSUW, \
    VZEROALL, \
    VZEROUPPER, \
    VPERMILTD2PS, \
    VPERMILMO2PS, \
    VPERMILMV2PS, \
    VPERMILTD2PD, \
    VPERMILMO2PD, \
    VPERMILMV2PD, \
    VFMADDPS, \
    VFMADDPD, \
    VFMADDSUBPS, \
    VFMADDSUBPD, \
    VFMSUBADDPS, \
    VFMSUBADDPD, \
    VFMSUBPS, \
    VFMSUBPD, \
    VFNMADDPD, \
    VFNMADDPS, \
    VFNMSUBPS, \
    VFNMSUBPD, \
    VFNMADDSS, \
    VFNMADDSD, \
    VFNMSUBSS, \
    VFNMSUBSD, \
    VFMADDSS, \
    VFMADDSD, \
    VFMSUBSS, \
    VFMSUBSD, \

    ;

      ENDHEAD iia ; End of module interface.
    [.text]

↑ MOVBE
  MovBig Endian (Move Data After Swapping Bytes)
Description
  MOVBE
Intel reference

  MOVBE reg16, mem16 | 0F 38 F0 /r
  MOVBE reg32, mem32 | 0F 38 F0 /r
  MOVBE reg64, mem64 | 0F 38 F0 /r
  MOVBE mem16, reg16 | 0F 38 F1 /r
  MOVBE mem32, reg32 | 0F 38 F1 /r
  MOVBE mem64, reg64 | 0F 38 F1 /r

Category
  gen,datamov
Operands
  Gvqp,Mvqp | Mvqp,Gvqp
Opcode
  0x0F38F0 /r | 0x0F38F1 /r
CPU
  C2++
Tested by
  t3780

    IiaMOVBE:: PROC
        IiRequire AMD,SPEC
        IiAllowModifier DATA
        IiDataSize SpecifyMem=OFF
        IiEmitOpcode 0x0F,0x38
        IiModRM /r
        IiDispatchFormat  r16.mem, r32.mem, r64.mem, mem.r16, mem.r32, mem.r64
    .r16.mem:
    .r32.mem:
    .r64.mem:
        IiOpEn RM
        IiEmitOpcode 0xF0
        RET
    .mem.r16:
    .mem.r32:
    .mem.r64:
        IiOpEn MR
        IiEmitOpcode 0xF1
        RET
      ENDP IiaMOVBE::

↑ ANDN
  Logical And-Not
Description
  ANDN
Intel reference

  ANDN reg32, reg32, reg/mem32 | VEX.NDS.LZ.0F38.W0 F2 /r
  ANDN reg64, reg64, reg/mem64 | C4 RXB.02 1.src1.0.00 F2 /r

    IiaANDN:: PROC
        IiEmitOpcode 0xF2
        IiRequire ABM
        IiAllowModifier DATA
        IiOpEn RVM
        IiModRM /r
        IiDispatchFormat  r32.r32.r32, r32.r32.mem, r64.r64.r64, r64.r64.mem
    .r32.r32.r32:
    .r32.r32.mem:
        IiEmitPrefix VEX.NDS.LZ.0F38.W0
        RET
    .r64.r64.r64:
    .r64.r64.mem:
        IiEmitPrefix VEX.NDS.LZ.0F38.W1
        RET
      ENDP IiaANDN::

↑ VAESENC
  AES Encryption round
Intel reference

  VAESENC xmm1, xmm2, xmm3/mem128 | C4 RXB.00010 X.src.0.01 DC /r

Tested by
  t4600

    IiaVAESENC:: PROC
        IiEmitOpcode 0xDC
    .op:IiRequire AES
        IiAllowModifier DATA
        IiOpEn RVM
        IiModRM /r
        IiEncoding DATA=OWORD
        IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
    .xmm.xmm.xmm:
    .xmm.xmm.mem:
        IiEmitPrefix VEX.NDS.128.66.0F38.WIG
        RET
      ENDP IiaVAESENC::

↑ VAESENCLAST
  AES Last Encryption Round
Intel reference

  VAESENCLAST xmm1, xmm2, xmm3/mem128 | C4 RXB.00010 X.src.0.01 DD /r

Tested by
  t4600

    IiaVAESENCLAST:: PROC
        IiEmitOpcode 0xDD
        JMP IiaVAESENC.op:
        RET
      ENDP IiaVAESENCLAST::

↑ VAESDEC
  AES Decryption Round
Intel reference

  VAESDEC xmm1, xmm2, xmm3/mem128 | C4 RXB.00010 X.src.0.01 DE /r

Tested by
  t4600

    IiaVAESDEC:: PROC
        IiEmitOpcode 0xDE
        JMP IiaVAESENC.op:
      ENDP IiaVAESDEC::

↑ VAESDECLAST
  AES Last Decryption Round
Intel reference

  VAESDECLAST xmm1, xmm2, xmm3/mem128 | C4 RXB.00010 X.src.0.01 DF /r

Tested by
  t4600

    IiaVAESDECLAST:: PROC
        IiEmitOpcode 0xDF
        JMP IiaVAESENC.op:
      ENDP IiaVAESDECLAST::

↑ VAESIMC
  AES InvMixColumn Transformation
Intel reference

  VAESIMC xmm1, xmm2/mem128 | VEX.128.66.0F38.WIG DB /r

Tested by
  t4600

    IiaVAESIMC:: PROC
        IiRequire AES
        IiAllowModifier DATA
        IiEmitOpcode 0xDB
        IiOpEn RM
        IiModRM /r
        IiEncoding DATA=OWORD
        IiDispatchFormat xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEmitPrefix VEX.128.66.0F38.WIG
        RET
      ENDP IiaVAESIMC::

↑ VAESKEYGENASSIST
  AES Assist Round Key Generation
Intel reference

  VAESKEYGENASSIST xmm1, xmm2/mem128, imm8 | VEX.128.66.0F3A.WIG DF /r ib

Tested by
  t4600

    IiaVAESKEYGENASSIST:: PROC
        IiRequire AES
        IiAllowModifier DATA,IMM
        IiEmitOpcode 0xDF
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3, BYTE
        IiEncoding DATA=OWORD
        IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm
    .xmm.xmm.imm:
    .xmm.mem.imm:
        IiEmitPrefix VEX.128.66.0F3A.WIG
        RET
      ENDP IiaVAESKEYGENASSIST::

↑ VPCMPESTRM
  Packed Compare Explicit Length Strings, Return Mask.
  Modifier DATA=D | DATA=Q specifies if the implicit length registers are EAX,EDX | RAX,RDX.
Intel reference

  VPCMPESTRM xmm1, xmm2/mem128, imm8 | C4 RXB.00011 X.1111.0.01 60 /r ib

Description
  PCMPESTRM
Category
  sse42,strtxt
Operands
  XMM0,Vdq,Wdq,...
Opcode
  0x660F3A60 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU
  C2++
Documented
  D43
Tested by
  t4610

    IiaVPCMPESTRM:: PROC
        IiEmitOpcode 0x60
    .op:IiRequire AMD,SSE4.2
        IiAllowModifier DATA,IMM
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3, BYTE
        IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm
    .xmm.xmm.imm:
    .xmm.mem.imm:
        JSt [EDI+II.MfgExplicit],iiMfgDATA_QWORD,.r64:
        IiEncoding DATA=DWORD
        IiEmitPrefix VEX.128.66.0F3A.W0
        RET
    .r64:IiEncoding DATA=QWORD
        IiEmitPrefix VEX.128.66.0F3A.W1
        RET
      ENDP IiaVPCMPESTRM::

↑ VPCMPESTRI
  Packed Compare Explicit Length Strings, Return Index.
  Modifier DATA=D | DATA=Q specifies if the implicit length registers are EAX,EDX | RAX,RDX.
Description
  PCMPESTRI
Intel reference

  VPCMPESTRI xmm1, xmm2/mem128, imm8 | C4 RXB.00011 X.1111.0.01 61 /r ib

Category
  sse42,strtxt
Operands
  rCX,Vdq,Wdq,...
Opcode
  0x660F3A61 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU
  C2++
Documented
  D43
Tested by
  t4610

    IiaVPCMPESTRI:: PROC
        IiEmitOpcode 0x61
        JMP IiaVPCMPESTRM.op
      ENDP IiaVPCMPESTRI::

↑ VPCMPISTRM
  Packed Compare Implicit Length Strings, Return Mask
Description
  PCMPISTRM
Intel reference

  VPCMPISTRM xmm1, xmm2/mem128, imm8 | C4 RXB.03 X.1111.0.01 62 /r ib

Category
  sse42,strtxt
Operands
  XMM0,Vdq,Wdq,Ib
Opcode
  0x660F3A62 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU
  C2++
Documented
  D43
Tested by
  t4610

    IiaVPCMPISTRM:: PROC
        IiEmitOpcode 0x62
    .op:IiRequire AMD,SSE4.2
        IiAllowModifier DATA,IMM
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3, BYTE
        IiDispatchFormat  xmm.xmm.imm, xmm.mem.imm
    .xmm.xmm.imm:
    .xmm.mem.imm:
        IiEmitPrefix VEX.128.66.0F3A.WIG
        RET
      ENDP IiaVPCMPISTRM::

↑ VPCMPISTRI
  Packed Compare Implicit Length Strings, Return Index
Description
  PCMPISTRI
Intel reference

  VPCMPISTRI xmm1, xmm2/mem128, imm8 | C4 RXB.03 X.1111.0.01 63 /r ib

Category
  sse42,strtxt
Operands
  rCX,Vdq,Wdq,Ib
Opcode
  0x660F3A63 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC, values:.....AP.
CPU
  C2++
Documented
  D43
Tested by
  t4610

    IiaVPCMPISTRI:: PROC
        IiEmitOpcode 0x63
        JMP IiaVPCMPISTRM.op:
      ENDP IiaVPCMPISTRI::

↑ VPSIGNB
  Packed SIGN Byte
Intel reference

  VPSIGNB xmm1, xmm2, xmm2/mem128 | C4 RXB.02 X.src1.0.01 08 /r
  VPSIGNB ymm1, ymm2, ymm2/mem256 | C4 RXB.02 X.src1.1.01 08 /r

Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3808 /r | 0x660F3808 /r
CPU
  C2+
Tested by
  t4620

    IiaVPSIGNB:: PROC
        IiEmitOpcode 0x08
    .op:IiRequire AMD, SSSE3
        IiAllowModifier DATA
        IiOpEn RVM
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem, ymm.ymm.ymm, ymm.ymm.mem
    .xmm.xmm.xmm:
    .xmm.xmm.mem:
        IiEncoding DATA=OWORD
        IiEmitPrefix VEX.NDS.128.66.0F38.WIG
        RET
    .ymm.ymm.ymm:
    .ymm.ymm.mem:
        IiEncoding DATA=YWORD
        IiEmitPrefix VEX.NDS.256.66.0F38.WIG
        RET
      ENDP IiaVPSIGNB::

↑ VPSIGNW
  Packed SIGN Wird
Intel reference

  VPSIGNW xmm1, xmm2, xmm3/mem128 | C4 RXB.02 X.src1.0.01 09 /r
  VPSIGNW ymm1, ymm2, ymm3/mem256 | C4 RXB.02 X.src1.1.01 09 /r

Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F3809 /r | 0x660F3809 /r
CPU
  C2+
Tested by
  t4620

    IiaVPSIGNW:: PROC
        IiEmitOpcode 0x09
        JMP IiaVPSIGNB.op:
      ENDP IiaVPSIGNW::

↑ VPSIGND
  Packed SIGN Dword
Intel reference

  VPSIGND xmm1, xmm2, xmm3/mem128 | C4 RXB.02 X.src1.0.01 0A /r
  VPSIGND ymm1, ymm2, ymm3/mem256 | C4 RXB.02 X.src1.1.01 0A /r

Category
  ssse3,simdint
Operands
  Pq,Qq | Vdq,Wdq
Opcode
  0x0F380A /r | 0x660F380A /r
CPU
  C2+
Tested by
  t4620

    IiaVPSIGND:: PROC
        IiEmitOpcode 0x0A
        JMP IiaVPSIGNB.op:
      ENDP IiaVPSIGND::

↑ VPTEST
  Logical Compare
Intel reference

  VPTEST xmm1, xmm2/mem128 | C4 RXB.00010 X.1111.0.01 17 /r
  VPTEST ymm1, ymm2/mem256 | C4 RXB.00010 X.1111.1.01 17 /r

Category
  sse41
Operands
  Vdq,Wdq
Opcode
  0x660F3817 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC, values:O..S.AP.
CPU
  C2++
Documented
  D43
Tested by
  t4630

    IiaVPTEST:: PROC
        IiEmitOpcode 0x17
    .op:IiRequire AMD
        IiAllowModifier DATA
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEncoding DATA=OWORD
        IiEmitPrefix VEX.128.66.0F38.WIG
        RET
    .ymm.ymm:
    .ymm.mem:
        IiEncoding DATA=YWORD
        IiEmitPrefix VEX.256.66.0F38.WIG
        RET
      ENDP IiaVPTEST::

↑ VTESTPS
  Packed Bit Test
Description
  VTESTPS
Intel reference

  VTESTPS xmm1, xmm2/mem128 | C4 RXB.02 0.1111.0.01 0E /r
  VTESTPS ymm1, ymm2/mem256 | C4 RXB.02 0.1111.1.01 0E /r

Opcode
  0x0E
Tested by
  t4630

    IiaVTESTPS:: PROC
        IiEmitOpcode 0x0E
        JMP IiaVPTEST.op:
      ENDP IiaVTESTPS::

↑ VTESTPD
  Packed Bit Test
Description
  VTESTPD
Intel reference

  VTESTPD xmm1, xmm2/mem128 | C4 RXB.02 0.1111.0.01 0F /r
  VTESTPD ymm1, ymm2/mem256 | C4 RXB.02 0.1111.1.01 0F /r

Opcode
  0x0F
Tested by
  t4630

    IiaVTESTPD:: PROC
        IiEmitOpcode 0x0F
        JMP IiaVPTEST.op:
      ENDP IiaVTESTPD::

↑ VPHMINPOSUW
  Packed Horizontal Word Minimum
Intel reference

  VPHMINPOSUW xmm1, xmm2/mem128 | C4 RXB.02 X.1111.0.01 41 /r

Category
  sse41,simdint,compar
Operands
  Vdq,Wdq
Opcode
  0x660F3841 /r
CPU
  C2++
Documented
  D43
Tested by
  t4635

    IiaVPHMINPOSUW:: PROC
        IiRequire AMD
        IiAllowModifier DATA
        IiEmitOpcode 0x41
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat  xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEmitPrefix VEX.128.66.0F38.WIG
        RET
      ENDP IiaVPHMINPOSUW::

↑ VZEROALL
  Zero All YMM Registers
Description
  VZEROALL
Intel reference

  VZEROALL | C4 RXB.01 X.1111.1.00 77

Opcode
  0x77
Tested by
  t4635

    IiaVZEROALL:: PROC
        IiEmitPrefix VEX.256.0F.WIG
    .pf:IiRequire AMD
        IiEmitOpcode 0x77
        IiDispatchFormat none
    .none:RET
      ENDP IiaVZEROALL::

↑ VZEROUPPER
  Zero All YMM Registers Upper
Description
  VZEROUPPER
Intel reference

  VZEROUPPER | C4 RXB.01 X.1111.0.00 77

Opcode
  0x77
Tested by
  t4635

    IiaVZEROUPPER:: PROC
        IiEmitPrefix VEX.128.0F.WIG
        JMP IiaVZEROALL.pf:
      ENDP IiaVZEROUPPER::

↑ VPERMILTD2PS
  Permute Two-Source Single-Precision Floating-Point Values, MatchToZero=0
Intel reference

  VPERMILTD2PS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 48 /r imm8
  VPERMILTD2PS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 48 /r imm8
  VPERMILTD2PS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 48 /r imm8
  VPERMILTD2PS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 48 /r imm8

Opcode
  0x48
Tested by
  t4640

    IiaVPERMILTD2PS:: PROC
        IiEmitOpcode 0x48
    .op:IiRequire AMD
        IiAllowModifier CODE,DATA
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.mem.xmm, xmm.xmm.xmm.mem, \
                          ymm.ymm.ymm.ymm, ymm.ymm.mem.ymm, ymm.ymm.ymm.mem
    .xmm.xmm.xmm.mem:
        IiEmitPrefix VEX.128.0F3A.W1
    .L: IiEncoding CODE=LONG
        IiSwap Operand3, Operand4
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.mem:
        IiEmitPrefix VEX.256.0F3A.W1
        JMP .L:
    .xmm.xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.xmm.mem:
    .xmm.xmm.mem.xmm:
        IiEmitPrefix VEX.128.0F3A.W0
    .S: IiEncoding CODE=SHORT
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.ymm:
        IiDispatchCode LONG=.ymm.ymm.ymm.mem:
    .ymm.ymm.mem.ymm:
        IiEmitPrefix VEX.256.0F3A.W0
        JMP .S:
      ENDP IiaVPERMILTD2PS::

↑ VPERMILMO2PS
  Permute Two-Source Single-Precision Floating-Point Values, MatchToZero=2
Intel reference

  VPERMILMO2PS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 48 /r imm8
  VPERMILMO2PS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 48 /r imm8
  VPERMILMO2PS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 48 /r imm8
  VPERMILMO2PS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 48 /r imm8

Opcode
  0x48
Tested by
  t4640

    IiaVPERMILMO2PS:: PROC
        IiEmitOpcode 0x48
        ORB [EDI+II.Imm2],2
        JMP IiaVPERMILTD2PS.op:
      ENDP IiaVPERMILMO2PS::

↑ VPERMILMV2PS
  Permute Two-Source Single-Precision Floating-Point Values, MatchToZero=3
Intel reference

  VPERMILMV2PS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 48 /r imm8
  VPERMILMV2PS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 48 /r imm8
  VPERMILMV2PS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 48 /r imm8
  VPERMILMV2PS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 48 /r imm8

Opcode
  0x48
Tested by
  t4640

    IiaVPERMILMV2PS:: PROC
        IiEmitOpcode 0x48
        ORB [EDI+II.Imm2],3
        JMP IiaVPERMILTD2PS.op:
      ENDP IiaVPERMILMV2PS::

↑ VPERMILTD2PD
  Permute Two-Source Double-Precision Floating- Point Values, MatchToZero=0
Intel reference

  VPERMILTD2PD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 49 /r imm8
  VPERMILTD2PD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 49 /r imm8
  VPERMILTD2PD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 49 /r imm8
  VPERMILTD2PD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 49 /r imm8

Opcode
  0x49
Tested by
  t4640

    IiaVPERMILTD2PD:: PROC
        IiEmitOpcode 0x49
        JMP IiaVPERMILTD2PS.op:
      ENDP IiaVPERMILTD2PD::

↑ VPERMILMO2PD
  Permute Two-Source Double-Precision Floating- Point Values, MatchToZero=2
Intel reference

  VPERMILMO2PD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 49 /r imm8
  VPERMILMO2PD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 49 /r imm8
  VPERMILMO2PD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 49 /r imm8
  VPERMILMO2PD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 49 /r imm8

Opcode
  0x49
Tested by
  t4640

    IiaVPERMILMO2PD:: PROC
        IiEmitOpcode 0x49
        ORB [EDI+II.Imm2],2
        JMP IiaVPERMILTD2PS.op:
      ENDP IiaVPERMILMO2PD::

↑ VPERMILMV2PD
  Permute Two-Source Double-Precision Floating- Point Values, MatchToZero=3
Intel reference

  VPERMILMV2PD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.00 49 /r imm8
  VPERMILMV2PD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.00 49 /r imm8
  VPERMILMV2PD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.00 49 /r imm8
  VPERMILMV2PD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.00 49 /r imm8

Opcode
  0x49
Tested by
  t4640

    IiaVPERMILMV2PD:: PROC
        IiEmitOpcode 0x49
        ORB [EDI+II.Imm2],3
        JMP IiaVPERMILTD2PS.op:
      ENDP IiaVPERMILMV2PD::

↑ VFMADDPS
  Multiply and Add Packed Single-Precision Floating-Point
Intel reference

  VFMADDPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 68 /r /is4
  VFMADDPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 68 /r /is4
  VFMADDPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 68 /r /is4
  VFMADDPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 68 /r /is4

Opcode
  0x68
Tested by
  t4650

    IiaVFMADDPS:: PROC
        IiEmitOpcode 0x68
    .op:IiRequire AMD,FMA
        IiAllowModifier CODE,DATA
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.mem.xmm, xmm.xmm.xmm.mem, \
                          ymm.ymm.ymm.ymm, ymm.ymm.mem.ymm, ymm.ymm.ymm.mem
    .xmm.xmm.xmm.mem:
        IiEmitPrefix VEX.128.66.0F3A.W1
    .L: IiEncoding CODE=LONG
        IiSwap Operand3, Operand4
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.mem:
        IiEmitPrefix VEX.256.66.0F3A.W1
        JMP .L:
    .xmm.xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.xmm.mem:
    .xmm.xmm.mem.xmm:
        IiEmitPrefix VEX.128.66.0F3A.W0
    .S: IiEncoding CODE=SHORT
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.ymm:
        IiDispatchCode LONG=.ymm.ymm.ymm.mem:
    .ymm.ymm.mem.ymm:
        IiEmitPrefix VEX.256.66.0F3A.W0
        JMP .S:
      ENDP IiaVFMADDPS::

↑ VFMADDPD
  Multiply and Add Packed Double-Precision Floating-Point
Intel reference

  VFMADDPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 69 /r /is4
  VFMADDPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 69 /r /is4
  VFMADDPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 69 /r /is4
  VFMADDPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 69 /r /is4

Opcode
  0x69
Tested by
  t4650

    IiaVFMADDPD:: PROC
        IiEmitOpcode 0x69
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMADDPD::

↑ VFMADDSUBPS
  Multiply with Alternating Add/Subtract of Packed Single-Precision Floating-Point
Intel reference

  VFMADDSUBPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 5C /r /is4
  VFMADDSUBPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 5C /r /is4
  VFMADDSUBPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 5C /r /is4
  VFMADDSUBPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 5C /r /is4

Opcode
  0x5C
Tested by
  t4650

    IiaVFMADDSUBPS:: PROC
        IiEmitOpcode 0x5C
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMADDSUBPS::

↑ VFMADDSUBPD
  Multiply with Alternating Add/Subtract of Packed Double-Precision Floating-Point
Intel reference

  VFMADDSUBPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 5D /r /is4
  VFMADDSUBPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 5D /r /is4
  VFMADDSUBPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 5D /r /is4
  VFMADDSUBPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 5D /r /is4

Opcode
  0x5D
Tested by
  t4650

    IiaVFMADDSUBPD:: PROC
        IiEmitOpcode 0x5D
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMADDSUBPD::

↑ VFMSUBADDPS
  Multiply with Alternating Subtract/Add of Packed Single-Precision Floating-Point
Intel reference

  VFMSUBADDPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 5E /r /is4
  VFMSUBADDPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 5E /r /is4
  VFMSUBADDPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 5E /r /is4
  VFMSUBADDPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 5E /r /is4

Opcode
  0x5E
Tested by
  t4655

    IiaVFMSUBADDPS:: PROC
        IiEmitOpcode 0x5E
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMSUBADDPS::

↑ VFMSUBADDPD
  Multiply with Alternating Subtract/Add of Packed Double-Precision Floating-Point
Intel reference

  VFMSUBADDPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 5F /r /is4
  VFMSUBADDPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 5F /r /is4
  VFMSUBADDPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 5F /r /is4
  VFMSUBADDPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 5F /r /is4

Opcode
  0x5F
Tested by
  t4655

    IiaVFMSUBADDPD:: PROC
        IiEmitOpcode 0x5F
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMSUBADDPD::

↑ VFMSUBPS
  Multiply and Subtract Packed Single-Precision Floating-Point
Intel reference

  VFMSUBPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 6C /r /is4
  VFMSUBPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 6C /r /is4
  VFMSUBPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 6C /r /is4
  VFMSUBPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 6C /r /is4

Opcode
  0x6C
Tested by
  t4655

    IiaVFMSUBPS:: PROC
        IiEmitOpcode 0x6C
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMSUBPS::

↑ VFMSUBPD
  Multiply and Subtract Packed Double-Precision Floating-Point
Intel reference

  VFMSUBPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 6D /r /is4
  VFMSUBPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 6D /r /is4
  VFMSUBPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 6D /r /is4
  VFMSUBPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 6D /r /is4

Opcode
  0x6D
Tested by
  t4655

    IiaVFMSUBPD:: PROC
        IiEmitOpcode 0x6D
        JMP IiaVFMADDPS.op:
      ENDP IiaVFMSUBPD::

↑ VFNMADDPD
  Negative Multiply and Add Packed Double-Precision Floating-Point
Intel reference

  VFNMADDPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 79 /r /is4
  VFNMADDPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 79 /r /is4
  VFNMADDPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 79 /r /is4
  VFNMADDPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 79 /r /is4

Opcode
  0x79
Tested by
  t4660

    IiaVFNMADDPD:: PROC
        IiEmitOpcode 0x79
        JMP IiaVFMADDPS.op:
      ENDP IiaVFNMADDPD::

↑ VFNMADDPS
  Negative Multiply and Add Packed Single-Precision Floating-Point
Intel reference

  VFNMADDPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 78 /r /is4
  VFNMADDPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 78 /r /is4
  VFNMADDPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 78 /r /is4
  VFNMADDPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 78 /r /is4

Opcode
  0x78
Tested by
  t4660

    IiaVFNMADDPS:: PROC
        IiEmitOpcode 0x78
        JMP IiaVFMADDPS.op:
      ENDP IiaVFNMADDPS::

↑ VFNMSUBPS
  Negative Multiply and Subtract Packed Single-Precision Floating-Point
Intel reference

  VFNMSUBPS xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 7C /r /is4
  VFNMSUBPS ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 7C /r /is4
  VFNMSUBPS xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 7C /r /is4
  VFNMSUBPS ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 7C /r /is4

Opcode
  0x7C
Tested by
  t4660

    IiaVFNMSUBPS:: PROC
        IiEmitOpcode 0x7C
        JMP IiaVFMADDPS.op:
      ENDP IiaVFNMSUBPS::

↑ VFNMSUBPD
  Negative Multiply and Subtract Packed Double-Precision Floating-Point
Intel reference

  VFNMSUBPD xmm1, xmm2, xmm3/mem128, xmm4 | C4 RXB.03 0.xsrc1.0.01 7D /r /is4
  VFNMSUBPD ymm1, ymm2, ymm3/mem256, ymm4 | C4 RXB.03 0.ysrc1.1.01 7D /r /is4
  VFNMSUBPD xmm1, xmm2, xmm3, xmm4/mem128 | C4 RXB.03 1.xsrc1.0.01 7D /r /is4
  VFNMSUBPD ymm1, ymm2, ymm3, ymm4/mem256 | C4 RXB.03 1.ysrc1.1.01 7D /r /is4

Opcode
  0x7D
Tested by
  t4660

    IiaVFNMSUBPD:: PROC
        IiEmitOpcode 0x7D
        JMP IiaVFMADDPS.op:
      ENDP IiaVFNMSUBPD::

↑ VFMADDSS
  Multiply and Add Scalar Single-Precision Floating-Point
Intel reference

  VFMADDSS xmm1, xmm2, xmm3/mem32, xmm4 | C4 RXB.03 0.xsrc1.0.01 6A /r /is4
  VFMADDSS xmm1, xmm2, xmm3, xmm4/mem32 | C4 RXB.03 1.xsrc1.0.01 6A /r /is4

Opcode
  0x6A
Tested by
  t4670

    IiaVFMADDSS:: PROC
        IiEmitOpcode 0x6A
    .op:IiRequire AMD, FMA
        IiAllowModifier CODE
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.mem.xmm, xmm.xmm.xmm.mem
    .xmm.xmm.xmm.mem:
        IiEncoding CODE=LONG
        IiSwap Operand3, Operand4
        IiOpEn RVM
        IiEmitPrefix VEX.128.66.0F3A.W1
        IiIs4 Operand4
        RET
    .xmm.xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.xmm.mem:
    .xmm.xmm.mem.xmm:
        IiEncoding CODE=SHORT
        IiOpEn RVM
        IiEmitPrefix VEX.128.66.0F3A.W0
        IiIs4 Operand4
        RET
      ENDP IiaVFMADDSS::

↑ VFMADDSD
  Multiply and Add Scalar Double-Precision Floating-Point
Intel reference

  VFMADDSD xmm1, xmm2, xmm3/mem64, xmm4 | C4 RXB.03 0.xsrc1.0.01 6B /r /is4
  VFMADDSD xmm1, xmm2, xmm3, xmm4/mem64 | C4 RXB.03 1.xsrc1.0.01 6B /r /is4

Opcode
  0x6B
Tested by
  t4670

    IiaVFMADDSD:: PROC
        IiEmitOpcode 0x6B
        JMP IiaVFMADDSS.op:
      ENDP IiaVFMADDSD::

↑ VFMSUBSS
  Multiply and Subtract Scalar Single-Precision Floating-Point
Intel reference

  VFMSUBSS xmm1, xmm2, xmm3/mem32, xmm4 | C4 RXB.03 0.xsrc1.0.01 6E /r /is4
  VFMSUBSS xmm1, xmm2, xmm3, xmm4/mem32 | C4 RXB.03 1.xsrc1.0.01 6E /r /is4

Opcode
  0x6E
Tested by
  t4670

    IiaVFMSUBSS:: PROC
        IiEmitOpcode 0x6E
        JMP IiaVFMADDSS.op:
      ENDP IiaVFMSUBSS::

↑ VFMSUBSD
  Multiply and Subtract Scalar Double-Precision Floating-Point
Intel reference

  VFMSUBSD xmm1, xmm2, xmm3/mem64, xmm4 | C4 RXB.03 0.xsrc1.0.01 6F /r /is4
  VFMSUBSD xmm1, xmm2, xmm3, xmm4/mem64 | C4 RXB.03 1.xsrc1.0.01 6F /r /is4

Opcode
  0x6F
Tested by
  t4670

    IiaVFMSUBSD:: PROC
        IiEmitOpcode 0x6F
        JMP IiaVFMADDSS.op:
      ENDP IiaVFMSUBSD::

↑ VFNMADDSS
  Negative Multiply and Add Scalar Single-Precision Floating-Point
Intel reference

  VFNMADDSS xmm1, xmm2, xmm3/mem32, xmm4 | C4 RXB.03 0.xsrc1.0.01 7A /r /is4
  VFNMADDSS xmm1, xmm2, xmm3, xmm4/mem32 | C4 RXB.03 1.xsrc1.0.01 7A /r /is4

Opcode
  0x7A
Tested by
  t4675

    IiaVFNMADDSS:: PROC
        IiEmitOpcode 0x7A
        JMP IiaVFMADDSS.op:
      ENDP IiaVFNMADDSS::

↑ VFNMADDSD
  Negative Multiply and Add Scalar Double-Precision Floating-Point
Intel reference

  VFNMADDSD xmm1, xmm2, xmm3/mem64, xmm4 | C4 RXB.03 0.xsrc1.0.01 7B /r /is4
  VFNMADDSD xmm1, xmm2, xmm3, xmm4/mem64 | C4 RXB.03 1.xsrc1.0.01 7B /r /is4

Opcode
  0x7B
Tested by
  t4675

    IiaVFNMADDSD:: PROC
        IiEmitOpcode 0x7B
        JMP IiaVFMADDSS.op:
      ENDP IiaVFNMADDSD::

↑ VFNMSUBSS
  Negative Multiply and Subtract Scalar Single-Precision Floating-Point
Intel reference

  VFNMSUBSS xmm1, xmm2, xmm3/mem32, xmm4 | C4 RXB.03 0.xsrc1.0.01 7E /r /is4
  VFNMSUBSS xmm1, xmm2, xmm3, xmm4/mem32 | C4 RXB.03 1.xsrc1.0.01 7E /r /is4

Opcode
  0x7E
Tested by
  t4675

    IiaVFNMSUBSS:: PROC
        IiEmitOpcode 0x7E
        JMP IiaVFMADDSS.op:
      ENDP IiaVFNMSUBSS::

↑ VFNMSUBSD
  Negative Multiply and Subtract Scalar Double-Precision Floating-Point
Intel reference

  VFNMSUBSD xmm1, xmm2, xmm3/mem64, xmm4 | C4 RXB.03 0.xsrc1.0.01 7F /r /is4
  VFNMSUBSD xmm1, xmm2, xmm3, xmm4/mem64 | C4 RXB.03 1.xsrc1.0.01 7F /r /is4

Opcode
  0x7F
Tested by
  t4675

    IiaVFNMSUBSD:: PROC
        IiEmitOpcode 0x7F
        JMP IiaVFMADDSS.op:
      ENDP IiaVFNMSUBSD::

      ENDPROGRAM iia

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