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# Test t5622: Machine instructions VPSRLW VPSRLD VPSRLQ VPSRLDQ

Tested procedures
  IizVPSRLW IizVPSRLD IizVPSRLQ IizVPSRLDQ

Source & expected listing t5622.htm.lst
  `| |EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=30,CPU=X64,SIMD=AVX512,EVEX=ON,MVEX=ON | |t5622 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF |[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE |00000000:C5E9D1CB | VPSRLW XMM1,XMM2,XMM3 |00000004:C5EDD1CB | VPSRLW YMM1,YMM2,XMM3 |00000008:C4E169D1CB | VPSRLW XMM1,XMM2,XMM3,PREFIX=VEX3 |0000000D:C4E16DD1CB | VPSRLW YMM1,YMM2,XMM3,PREFIX=VEX3 |00000012:62F16D8CD1CB | VPSRLW XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |00000018:62F16D2CD1CB | VPSRLW YMM1,YMM2,XMM3,MASK=K4 |0000001E:62F16D4CD1CB | VPSRLW ZMM1,ZMM2,XMM3,MASK=K4 |00000024:C5E9D14D40 | VPSRLW XMM1,XMM2,[RBP+40h] |00000029:C5EDD14D40 | VPSRLW YMM1,YMM2,[RBP+40h] |0000002E:C4E169D14D40 | VPSRLW XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |00000034:C4E16DD14D40 | VPSRLW YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |0000003A:62F16D0CD14D04<4 | VPSRLW XMM1,XMM2,[RBP+40h],MASK=K4 |00000041:62F16DACD14D04<4 | VPSRLW YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000048:62F16D4CD14D04<4 | VPSRLW ZMM1,ZMM2,[RBP+40h],MASK=K4 |0000004F:62F17508715504<403 | VPSRLW XMM1,[RBP+40h],3 |00000057:62F1752C715502<503 | VPSRLW YMM1,[RBP+40h],3,MASK=K4 |0000005F:62F175CC715501<603 | VPSRLW ZMM1,[RBP+40h],3,MASK=K4,ZEROING=ON |00000067:C5E9D2CB | VPSRLD XMM1,XMM2,XMM3 |0000006B:C5EDD2CB | VPSRLD YMM1,YMM2,XMM3 |0000006F:C4E169D2CB | VPSRLD XMM1,XMM2,XMM3,PREFIX=VEX3 |00000074:C4E16DD2CB | VPSRLD YMM1,YMM2,XMM3,PREFIX=VEX3 |00000079:62F16D0CD2CB | VPSRLD XMM1,XMM2,XMM3,MASK=K4 |0000007F:62F16D2CD2CB | VPSRLD YMM1,YMM2,XMM3,MASK=K4 |00000085:62F16DCCD2CB | VPSRLD ZMM1,ZMM2,XMM3,MASK=K4,ZEROING=ON |0000008B:62F1712C72D203 | VPSRLD ZMM1,ZMM2,3,MASK=K4,EH=OFF,OPER=2 ; MVEX {badc}. |00000092:C5E9D24D40 | VPSRLD XMM1,XMM2,[RBP+40h] |00000097:C5EDD24D40 | VPSRLD YMM1,YMM2,[RBP+40h] |0000009C:C4E169D24D40 | VPSRLD XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |000000A2:C4E16DD24D40 | VPSRLD YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |000000A8:62F16D0CD24D04<4 | VPSRLD XMM1,XMM2,[RBP+40h],MASK=K4 |000000AF:62F16DACD24D04<4 | VPSRLD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |000000B6:62F16D4CD24D04<4 | VPSRLD ZMM1,ZMM2,[RBP+40h],MASK=K4 |000000BD:62F17508725504<403 | VPSRLD XMM1,[RBP+40h],3 |000000C5:62F17528725502<503 | VPSRLD YMM1,[RBP+40h],3 |000000CD:62F17548725501<603 | VPSRLD ZMM1,[RBP+40h],3 |000000D5:62F17518725510<203 | VPSRLD XMM1,[RBP+40h],3,BCST=ON |000000DD:62F17538725510<203 | VPSRLD YMM1,[RBP+40h],3,BCST=ON |000000E5:62F17558725510<203 | VPSRLD ZMM1,[RBP+40h],3,BCST=ON |000000ED:62F175CC725501<603 | VPSRLD ZMM1,[RBP+40h],3,MASK=K4,ZEROING=ON |000000F5:62F1710C725501<603 | VPSRLD ZMM1,[RBP+40h],3,MASK=K4,PREFIX=MVEX,OPER=0 ; {16to16}. |000000FD:62F1711C725510<203 | VPSRLD ZMM1,[RBP+40h],3,MASK=K4,PREFIX=MVEX,OPER=1 ; {1to16}. |00000105:62F1712C725504<403 | VPSRLD ZMM1,[RBP+40h],3,MASK=K4,PREFIX=MVEX,OPER=2 ; {4to16}. |0000010D:62F1716C725502<503 | VPSRLD ZMM1,[RBP+40h],3,MASK=K4,PREFIX=MVEX,OPER=6 ; {uint16}. |00000115:C5E9D3CB | VPSRLQ XMM1,XMM2,XMM3 |00000119:C5EDD3CB | VPSRLQ YMM1,YMM2,XMM3 |0000011D:C4E169D3CB | VPSRLQ XMM1,XMM2,XMM3,PREFIX=VEX3 |00000122:C4E16DD3CB | VPSRLQ YMM1,YMM2,XMM3,PREFIX=VEX3 |00000127:62F1ED8CD3CB | VPSRLQ XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |0000012D:62F1ED2CD3CB | VPSRLQ YMM1,YMM2,XMM3,MASK=K4 |00000133:62F1ED4CD3CB | VPSRLQ ZMM1,ZMM2,XMM3,MASK=K4 |00000139:C5E9D34D40 | VPSRLQ XMM1,XMM2,[RBP+40h] |0000013E:C5EDD34D40 | VPSRLQ YMM1,YMM2,[RBP+40h] |00000143:C4E169D34D40 | VPSRLQ XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |00000149:C4E16DD34D40 | VPSRLQ YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |0000014F:62F1ED0CD34D04<4 | VPSRLQ XMM1,XMM2,[RBP+40h],MASK=K4 |00000156:62F1EDACD34D04<4 | VPSRLQ YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000015D:62F1ED4CD34D04<4 | VPSRLQ ZMM1,ZMM2,[RBP+40h],MASK=K4 |00000164:62F1F508735504<403 | VPSRLQ XMM1,[RBP+40h],3 |0000016C:62F1F528735502<503 | VPSRLQ YMM1,[RBP+40h],3 |00000174:62F1F548735501<603 | VPSRLQ ZMM1,[RBP+40h],3 |0000017C:62F1F518735508<303 | VPSRLQ XMM1,[RBP+40h],3,BCST=ON |00000184:62F1F538735508<303 | VPSRLQ YMM1,[RBP+40h],3,BCST=ON |0000018C:62F1F558735508<303 | VPSRLQ ZMM1,[RBP+40h],3,BCST=ON |00000194:62F1F5CC735501<603 | VPSRLQ ZMM1,[RBP+40h],3,MASK=K4,ZEROING=ON |0000019C:C5F173DA03 | VPSRLDQ XMM1,XMM2,3 |000001A1:C5F573DA03 | VPSRLDQ YMM1,YMM2,3 |000001A6:C4E17173DA03 | VPSRLDQ XMM1,XMM2,3,PREFIX=VEX3 |000001AC:C4E17573DA03 | VPSRLDQ YMM1,YMM2,3,PREFIX=VEX3 |000001B2:62F1750873DA03 | VPSRLDQ XMM1,XMM2,3,PREFIX=EVEX |000001B9:62F1752873DA03 | VPSRLDQ YMM1,YMM2,3,PREFIX=EVEX |000001C0:62F1754873DA03 | VPSRLDQ ZMM1,ZMM2,3 |000001C7:62F17508735D04<403 | VPSRLDQ XMM1,[RBP+40h],3 |000001CF:62F17528735D02<503 | VPSRLDQ YMM1,[RBP+40h],3 |000001D7:62F17548735D01<603 | VPSRLDQ ZMM1,[RBP+40h],3 | |ENDPROGRAM t5622`

Expected messages t5622.out
  `I0180 Assembling source file "t5622.htm". I0270 Assembling source "t5622". I0310 Assembling source pass 1. I0330 Assembling source pass 2 - final. I0470 Assembling program "t5622". "t5622.htm"{58} I0510 Assembling program pass 1. "t5622.htm"{58} I0530 Assembling program pass 2 - final. "t5622.htm"{58} I0660 16bit TINY BIN file "t5622.bin" created, size=479. "t5622.htm"{134} I0650 Program "t5622" assembled in 2 passes with errorlevel 0. "t5622.htm"{134} I0750 Source "t5622" (152 lines) assembled in 2 passes with errorlevel 0. I0860 Listing file "t5622.htm.lst" created, size=5149. I0990 EuroAssembler terminated with errorlevel 0.`

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