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# Test t5696: Machine instructions VPACKSSWB VPACKUSWB VPACKSSDW VPACKUSDW

Tested procedures
  IiyVPACKSSWB IiyVPACKUSWB IiyVPACKSSDW IiyVPACKUSDW

Source & expected listing t5696.htm.lst
  `| | EUROASM LIST=ON, DUMP=ON, DUMPWIDTH=28, CPU=X64, SIMD=AVX512,EVEX=ON | |t5696 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF |[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE |00000000:C5E963CB | VPACKSSWB XMM1,XMM2,XMM3 |00000004:C4E16963CB | VPACKSSWB XMM1,XMM2,XMM3,PREFIX=VEX3 |00000009:62F16D8C63CB | VPACKSSWB XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |0000000F:C5ED63CB | VPACKSSWB YMM1,YMM2,YMM3 |00000013:C4E16D63CB | VPACKSSWB YMM1,YMM2,YMM3,PREFIX=VEX3 |00000018:62F16DAC63CB | VPACKSSWB YMM1,YMM2,YMM3,MASK=K4,ZEROING=ON |0000001E:62F16DCC63CB | VPACKSSWB ZMM1,ZMM2,ZMM3,MASK=K4,ZEROING=ON |00000024:C5E9634D40 | VPACKSSWB XMM1,XMM2,[RBP+40h] |00000029:C4E169634D40 | VPACKSSWB XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |0000002F:62F16D8C634D04<4 | VPACKSSWB XMM1,XMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000036:C5ED634D40 | VPACKSSWB YMM1,YMM2,[RBP+40h] |0000003B:C4E16D634D40 | VPACKSSWB YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |00000041:62F16DAC634D02<5 | VPACKSSWB YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000048:62F16DCC634D01<6 | VPACKSSWB ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000004F:C5E967CB | VPACKUSWB XMM1,XMM2,XMM3 |00000053:C4E16967CB | VPACKUSWB XMM1,XMM2,XMM3,PREFIX=VEX3 |00000058:62F16D8C67CB | VPACKUSWB XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |0000005E:C5ED67CB | VPACKUSWB YMM1,YMM2,YMM3 |00000062:C4E16D67CB | VPACKUSWB YMM1,YMM2,YMM3,PREFIX=VEX3 |00000067:62F16DAC67CB | VPACKUSWB YMM1,YMM2,YMM3,MASK=K4,ZEROING=ON |0000006D:62F16DCC67CB | VPACKUSWB ZMM1,ZMM2,ZMM3,MASK=K4,ZEROING=ON |00000073:C5E9674D40 | VPACKUSWB XMM1,XMM2,[RBP+40h] |00000078:C4E169674D40 | VPACKUSWB XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |0000007E:62F16D8C674D04<4 | VPACKUSWB XMM1,XMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000085:C5ED674D40 | VPACKUSWB YMM1,YMM2,[RBP+40h] |0000008A:C4E16D674D40 | VPACKUSWB YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |00000090:62F16DAC674D02<5 | VPACKUSWB YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000097:62F16DCC674D01<6 | VPACKUSWB ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000009E:C5E96BCB | VPACKSSDW XMM1,XMM2,XMM3 |000000A2:C4E1696BCB | VPACKSSDW XMM1,XMM2,XMM3,PREFIX=VEX3 |000000A7:62F16D8C6BCB | VPACKSSDW XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |000000AD:C5ED6BCB | VPACKSSDW YMM1,YMM2,YMM3 |000000B1:C4E16D6BCB | VPACKSSDW YMM1,YMM2,YMM3,PREFIX=VEX3 |000000B6:62F16DAC6BCB | VPACKSSDW YMM1,YMM2,YMM3,MASK=K4,ZEROING=ON |000000BC:62F16DCC6BCB | VPACKSSDW ZMM1,ZMM2,ZMM3,MASK=K4,ZEROING=ON |000000C2:C5E96B4D40 | VPACKSSDW XMM1,XMM2,[RBP+40h] |000000C7:C4E1696B4D40 | VPACKSSDW XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |000000CD:62F16D8C6B4D04<4 | VPACKSSDW XMM1,XMM2,[RBP+40h],MASK=K4,ZEROING=ON |000000D4:C5ED6B4D40 | VPACKSSDW YMM1,YMM2,[RBP+40h] |000000D9:C4E16D6B4D40 | VPACKSSDW YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |000000DF:62F16DAC6B4D02<5 | VPACKSSDW YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |000000E6:62F16D086B4D04<4 | VPACKSSDW XMM1,XMM2,[RBP+40h],BCST=OFF |000000ED:62F16D286B4D02<5 | VPACKSSDW YMM1,YMM2,[RBP+40h],BCST=OFF |000000F4:62F16D486B4D01<6 | VPACKSSDW ZMM1,ZMM2,[RBP+40h],BCST=OFF |000000FB:62F16D186B4D10<2 | VPACKSSDW XMM1,XMM2,[RBP+40h],BCST=ON |00000102:62F16D386B4D10<2 | VPACKSSDW YMM1,YMM2,[RBP+40h],BCST=ON |00000109:62F16D586B4D10<2 | VPACKSSDW ZMM1,ZMM2,[RBP+40h],BCST=ON |00000110:C4E2692BCB | VPACKUSDW XMM1,XMM2,XMM3 |00000115:C4E2692BCB | VPACKUSDW XMM1,XMM2,XMM3,PREFIX=VEX3 |0000011A:62F26D8C2BCB | VPACKUSDW XMM1,XMM2,XMM3,MASK=K4,ZEROING=ON |00000120:C4E26D2BCB | VPACKUSDW YMM1,YMM2,YMM3 |00000125:C4E26D2BCB | VPACKUSDW YMM1,YMM2,YMM3,PREFIX=VEX3 |0000012A:62F26DAC2BCB | VPACKUSDW YMM1,YMM2,YMM3,MASK=K4,ZEROING=ON |00000130:62F26DCC2BCB | VPACKUSDW ZMM1,ZMM2,ZMM3,MASK=K4,ZEROING=ON |00000136:C4E2692B4D40 | VPACKUSDW XMM1,XMM2,[RBP+40h] |0000013C:C4E2692B4D40 | VPACKUSDW XMM1,XMM2,[RBP+40h],PREFIX=VEX3 |00000142:62F26D8C2B4D04<4 | VPACKUSDW XMM1,XMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000149:C4E26D2B4D40 | VPACKUSDW YMM1,YMM2,[RBP+40h] |0000014F:C4E26D2B4D40 | VPACKUSDW YMM1,YMM2,[RBP+40h],PREFIX=VEX3 |00000155:62F26DAC2B4D02<5 | VPACKUSDW YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000015C:62F26D082B4D04<4 | VPACKUSDW XMM1,XMM2,[RBP+40h],BCST=OFF |00000163:62F26D282B4D02<5 | VPACKUSDW YMM1,YMM2,[RBP+40h],BCST=OFF |0000016A:62F26D482B4D01<6 | VPACKUSDW ZMM1,ZMM2,[RBP+40h],BCST=OFF |00000171:62F26D182B4D10<2 | VPACKUSDW XMM1,XMM2,[RBP+40h],BCST=ON |00000178:62F26D382B4D10<2 | VPACKUSDW YMM1,YMM2,[RBP+40h],BCST=ON |0000017F:62F26D582B4D10<2 | VPACKUSDW ZMM1,ZMM2,[RBP+40h],BCST=ON | |ENDPROGRAM t5696`

Expected messages t5696.out
  `I0180 Assembling source file "t5696.htm". I0270 Assembling source "t5696". I0310 Assembling source pass 1. I0330 Assembling source pass 2 - final. I0470 Assembling program "t5696". "t5696.htm"{58} I0510 Assembling program pass 1. "t5696.htm"{58} I0530 Assembling program pass 2 - final. "t5696.htm"{58} I0660 16bit TINY BIN file "t5696.bin" created, size=390. "t5696.htm"{126} I0650 Program "t5696" assembled in 2 passes with errorlevel 0. "t5696.htm"{126} I0750 Source "t5696" (144 lines) assembled in 2 passes with errorlevel 0. I0860 Listing file "t5696.htm.lst" created, size=4830. I0990 EuroAssembler terminated with errorlevel 0.`

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