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# iix.htm
Enumerations
IixList
Instruction handlers
BLCFILL BLCI BLCIC BLCMSK BLCS BLSFILL BLSIC LLWPCB LWPINS LWPVAL SLWPCB T1MSKC TZMSK VFRCZPD VFRCZPS VFRCZSD VFRCZSS VPCMOV VPCOMB VPCOMD VPCOMEQB VPCOMEQD VPCOMEQQ VPCOMEQUB VPCOMEQUD VPCOMEQUQ VPCOMEQUW VPCOMEQW VPCOMFALSEB VPCOMFALSED VPCOMFALSEQ VPCOMFALSEUB VPCOMFALSEUD VPCOMFALSEUQ VPCOMFALSEUW VPCOMFALSEW VPCOMGEB VPCOMGED VPCOMGEQ VPCOMGEUB VPCOMGEUD VPCOMGEUQ VPCOMGEUW VPCOMGEW VPCOMGTB VPCOMGTD VPCOMGTQ VPCOMGTUB VPCOMGTUD VPCOMGTUQ VPCOMGTUW VPCOMGTW VPCOMLEB VPCOMLED VPCOMLEQ VPCOMLEUB VPCOMLEUD VPCOMLEUQ VPCOMLEUW VPCOMLEW VPCOMLTB VPCOMLTD VPCOMLTQ VPCOMLTUB VPCOMLTUD VPCOMLTUQ VPCOMLTUW VPCOMLTW VPCOMNEQB VPCOMNEQD VPCOMNEQQ VPCOMNEQUB VPCOMNEQUD VPCOMNEQUQ VPCOMNEQUW VPCOMNEQW VPCOMQ VPCOMTRUEB VPCOMTRUED VPCOMTRUEQ VPCOMTRUEUB VPCOMTRUEUD VPCOMTRUEUQ VPCOMTRUEUW VPCOMTRUEW VPCOMUB VPCOMUD VPCOMUQ VPCOMUW VPCOMW VPHADDBD VPHADDBQ VPHADDBW VPHADDDQ VPHADDUBD VPHADDUBQ VPHADDUBW VPHADDUDQ VPHADDUWD VPHADDUWQ VPHADDWD VPHADDWQ VPHSUBBW VPHSUBDQ VPHSUBWD VPMACSDD VPMACSDQH VPMACSDQL VPMACSSDD VPMACSSDQH VPMACSSDQL VPMACSSWD VPMACSSWW VPMACSWD VPMACSWW VPMADCSSWD VPMADCSWD VPPERM VPROTB VPROTD VPROTQ VPROTW VPSHAB VPSHAD VPSHAQ VPSHAW VPSHLB VPSHLD VPSHLQ VPSHLW

↑ IixHandlers
  assemble AMD-specifix instructions encodable with XOP prefix only.
See also
  IiHandlers, [AMDVol6].

    iix PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
        INCLUDEHEAD euroasm.htm, \  Interface (structures, symbols and macros) of other modules used in this source.
                    ea.htm,eaopt.htm,exp.htm,ii.htm,msg.htm,pgm.htm,pgmopt.htm,sss.htm,stm.htm,sym.htm

    iix HEAD ; Start of module interface.

↑ %IixList
  enumerates machine instructions of this family which €ASM can assemble.
  Each instruction declared in `%IixList` requires the corresponding handler in this file.
See also
  DictLookupIi

    %IixList %SET \
    BLCFILL, \
    BLSFILL, \
    BLCS, \
    TZMSK, \
    BLCIC, \
    BLSIC, \
    T1MSKC, \
    BLCMSK, \
    BLCI, \
    LLWPCB, \
    SLWPCB, \
    LWPINS, \
    LWPVAL, \
    VPMACSSWW, \
    VPMACSSWD, \
    VPMACSSDQL, \
    VPMACSSDD, \
    VPMACSSDQH, \
    VPMACSWW, \
    VPMACSWD, \
    VPMACSDQL, \
    VPMACSDD, \
    VPMACSDQH, \
    VPMADCSSWD, \
    VPMADCSWD, \
    VPPERM, \
    VPROTB, \
    VPROTW, \
    VPROTD, \
    VPROTQ, \
    VPSHLB, \
    VPSHLW, \
    VPSHLD, \
    VPSHLQ, \
    VPSHAB, \
    VPSHAW, \
    VPSHAD, \
    VPSHAQ, \
    VPCMOV, \
    VFRCZPS, \
    VFRCZPD, \
    VFRCZSS, \
    VFRCZSD, \
    VPHADDBW, \
    VPHADDBD, \
    VPHADDBQ, \
    VPHADDWD, \
    VPHADDWQ, \
    VPHADDUBW, \
    VPHADDUBD, \
    VPHADDUBQ, \
    VPHADDUWD, \
    VPHADDUWQ, \
    VPHADDDQ, \
    VPHADDUDQ, \
    VPHSUBBW, \
    VPHSUBWD, \
    VPHSUBDQ, \
    VPCOMB, \
    VPCOMLTB, \
    VPCOMLEB, \
    VPCOMGTB, \
    VPCOMGEB, \
    VPCOMEQB, \
    VPCOMNEQB, \
    VPCOMFALSEB, \
    VPCOMTRUEB, \
    VPCOMW, \
    VPCOMLTW, \
    VPCOMLEW, \
    VPCOMGTW, \
    VPCOMGEW, \
    VPCOMEQW, \
    VPCOMNEQW, \
    VPCOMFALSEW, \
    VPCOMTRUEW, \
    VPCOMD, \
    VPCOMLTD, \
    VPCOMLED, \
    VPCOMGTD, \
    VPCOMGED, \
    VPCOMEQD, \
    VPCOMNEQD, \
    VPCOMFALSED, \
    VPCOMTRUED, \
    VPCOMQ, \
    VPCOMLTQ, \
    VPCOMLEQ, \
    VPCOMGTQ, \
    VPCOMGEQ, \
    VPCOMEQQ, \
    VPCOMNEQQ, \
    VPCOMFALSEQ, \
    VPCOMTRUEQ, \
    VPCOMUB, \
    VPCOMLTUB, \
    VPCOMLEUB, \
    VPCOMGTUB, \
    VPCOMGEUB, \
    VPCOMEQUB, \
    VPCOMNEQUB, \
    VPCOMFALSEUB, \
    VPCOMTRUEUB, \
    VPCOMUW, \
    VPCOMLTUW, \
    VPCOMLEUW, \
    VPCOMGTUW, \
    VPCOMGEUW, \
    VPCOMEQUW, \
    VPCOMNEQUW, \
    VPCOMFALSEUW, \
    VPCOMTRUEUW, \
    VPCOMUD, \
    VPCOMLTUD, \
    VPCOMLEUD, \
    VPCOMGTUD, \
    VPCOMGEUD, \
    VPCOMEQUD, \
    VPCOMNEQUD, \
    VPCOMFALSEUD, \
    VPCOMTRUEUD, \
    VPCOMUQ, \
    VPCOMLTUQ, \
    VPCOMLEUQ, \
    VPCOMGTUQ, \
    VPCOMGEUQ, \
    VPCOMEQUQ, \
    VPCOMNEQUQ, \
    VPCOMFALSEUQ, \
    VPCOMTRUEUQ, \

    ;

      ENDHEAD iix ; End of module interface.

↑ BLCFILL
  Fill From Lowest Clear Bit
AMD reference

  BLCFILL reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /1
  BLCFILL reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /1

Tested by
  t4510

    IixBLCFILL:: PROC
        IiModRM /1
    .rm:IiRequire AMD, XOP
        IiAllowModifier DATA
        IiOpEn VM
        IiEmitOpcode 0x01
        IiDispatchFormat  r32.r32, r32.mem, r64.r64, r64.mem
    .r32.r32:
    .r32.mem:
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
    .r64.r64:
    .r64.mem:
        IiEmitPrefix XOP.MAP9.W1.L0
        RET
      ENDP IixBLCFILL::

↑ BLSFILL
  Fill From Lowest Set Bit
AMD reference

  BLSFILL reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /2
  BLSFILL reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /2

Tested by
  t4510

    IixBLSFILL:: PROC
        IiModRM /2
        JMP IixBLCFILL.rm:
      ENDP IixBLSFILL::

↑ BLCS
  Set Lowest Clear Bit
AMD reference

  BLCS reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /3
  BLCS reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /3

Tested by
  t4510

    IixBLCS:: PROC
        IiModRM /3
        JMP IixBLCFILL.rm:
      ENDP IixBLCS::

↑ TZMSK
  Mask From Trailing Zeros
AMD reference

  TZMSK reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /4
  TZMSK reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /4

Tested by
  t4510

    IixTZMSK:: PROC
        IiModRM /4
        JMP IixBLCFILL.rm:
      ENDP IixTZMSK::

↑ BLCIC
  Isolate Lowest Clear Bit and Complement
AMD reference

  BLCIC reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /5
  BLCIC reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /5

Tested by
  t4510

    IixBLCIC:: PROC
        IiModRM /5
        JMP IixBLCFILL.rm:
      ENDP IixBLCIC::

↑ BLSIC
  Isolate Lowest Set Bit and Complement
AMD reference

  BLSIC reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /6
  BLSIC reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /6

Tested by
  t4510

    IixBLSIC:: PROC
        IiModRM /6
        JMP IixBLCFILL.rm:
      ENDP IixBLSIC::

↑ T1MSKC
  Inverse Mask From Trailing Ones
AMD reference

  T1MSKC reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 01 /7
  T1MSKC reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 01 /7

Tested by
  t4510

    IixT1MSKC:: PROC
        IiModRM /7
        JMP IixBLCFILL.rm:
      ENDP IixT1MSKC::

↑ BLCMSK
  Mask From Lowest Clear Bit
AMD reference

  BLCMSK reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 02 /1
  BLCMSK reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 02 /1

Tested by
  t4512

    IixBLCMSK:: PROC
        IiModRM /1
    .rm:IiRequire AMD, XOP, PROT
        IiAllowModifier DATA
        IiOpEn VM
        IiEmitOpcode 0x02
        IiDispatchFormat  r32.r32, r32.mem, r64.r64, r64.mem
    .r32.r32:
    .r32.mem:
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
    .r64.r64:
    .r64.mem:
        IiEmitPrefix XOP.MAP9.W1.L0
        RET
      ENDP IixBLCMSK::

↑ BLCI
  Isolate Lowest Clear Bit
AMD reference

  BLCI reg32, reg/mem32 | 8F RXB.09 0.dest.0.00 02 /6
  BLCI reg64, reg/mem64 | 8F RXB.09 1.dest.0.00 02 /6

Tested by
  t4512

    IixBLCI:: PROC
        IiModRM /6
        JMP IixBLCMSK.rm:
      ENDP IixBLCI::

↑ LLWPCB
  Load Lightweight Profiling Control Block Address
AMD reference

  LLWPCB reg32 | 8F RXB.09 0.1111.0.00 12 /0
  LLWPCB reg64 | 8F RXB.09 1.1111.0.00 12 /0

Tested by
  t4512

    IixLLWPCB:: PROC
         IiModRM /0
    .rm: IiRequire AMD, XOP, PROT, LWP
         IiOpEn M
         IiEmitOpcode 0x12
         IiDispatchFormat  r32, r64
    .r32:IiEmitPrefix XOP.MAP9.W0.L0
         RET
    .r64:IiEmitPrefix XOP.MAP9.W1.L0
         RET
      ENDP IixLLWPCB::

↑ SLWPCB
  Store Lightweight Profiling Control Block Address
AMD reference

  SLWPCB reg32 | 8F RXB.09 0.1111.0.00 12 /1
  SLWPCB reg64 | 8F RXB.09 1.1111.0.00 12 /1

Tested by
  t4512

    IixSLWPCB:: PROC
        IiModRM /1
        JMP IixLLWPCB.rm:
      ENDP IixSLWPCB::

↑ LWPINS
  Lightweight Profiling Insert Record
AMD reference

  LWPINS reg32.vvvv, reg/mem32, imm32 | 8F RXB.0A 0.src1.0.00 12 /0 /imm32
  LWPINS reg64.vvvv, reg/mem32, imm32 | 8F RXB.0A 1.src1.0.00 12 /0 /imm32

Tested by
  t4512

    IixLWPINS:: PROC
        IiModRM /0
    .rm:IiRequire AMD, XOP, PROT, LWP
        IiAllowModifier DATA,IMM
        IiOpEn VM
        IiEmitOpcode 0x12
        IiEmitImm Operand3, DWORD
        IiDispatchFormat  r32.r32.imm, r32.mem.imm, r64.r32.imm, r64.r64.imm, r64.mem.imm
    .r32.r32.imm:
    .r32.mem.imm:
        IiEmitPrefix XOP.MAP10.W0.L0
        RET
    .r64.r64.imm:
    .r64.r32.imm:
    .r64.mem.imm:
        IiEmitPrefix XOP.MAP10.W1.L0
        RET
      ENDP IixLWPINS::

↑ LWPVAL
  Lightweight Profiling Insert Value
AMD reference

  LWPVAL reg32.vvvv, reg/mem32, imm32 | 8F RXB.0A 0.src1.0.00 12 /1 /imm32
  LWPVAL reg64.vvvv, reg/mem32, imm32 | 8F RXB.0A 1.src1.0.00 12 /1 /imm32

Tested by
  t4512

    IixLWPVAL:: PROC
        IiModRM /1
        JMP IixLWPINS.rm:
      ENDP IixLWPVAL::

↑ VPMACSSWW
  Packed Multiply Accumulate Signed Word to Signed Word with Saturation
AMD reference

  VPMACSSWW xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 85 /r /is4

Tested by
  t4520

    IixVPMACSSWW:: PROC
        IiEmitOpcode 0x85
    .op:IiRequire AMD, XOP
        IiOpEn RVM
        IiModRM /r
        IiIs4 Operand4
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.mem.xmm
    .xmm.xmm.xmm.xmm:
    .xmm.xmm.mem.xmm:
        IiEmitPrefix XOP.MAP8.W0.L0
        RET
      ENDP IixVPMACSSWW::

↑ VPMACSSWD
  Packed Multiply Accumulate Signed Word to Signed Doubleword with Saturation
AMD reference

  VPMACSSWD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 86 /r /is4

Tested by
  t4520

    IixVPMACSSWD:: PROC
        IiEmitOpcode 0x86
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSSWD::

↑ VPMACSSDQL
  Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword with Saturation
AMD reference

  VPMACSSDQL xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 87 /r /is4

Tested by
  t4520

    IixVPMACSSDQL:: PROC
        IiEmitOpcode 0x87
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSSDQL::

↑ VPMACSSDD
  Packed Multiply Accumulate Signed Doubleword to Signed Doubleword with Saturation
AMD reference

  VPMACSSDD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 8E /r /is4

Tested by
  t4520

    IixVPMACSSDD:: PROC
        IiEmitOpcode 0x8E
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSSDD::

↑ VPMACSSDQH
  Packed Multiply Accumulate Signed High Doubleword to Signed Quadword with Saturation
AMD reference

  VPMACSSDQH xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 8F /r is4

Tested by
  t4520

    IixVPMACSSDQH:: PROC
        IiEmitOpcode 0x8F
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSSDQH::

↑ VPMACSWW
  Packed Multiply Accumulate Signed Word to Signed Word
AMD reference

  VPMACSWW xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 95 /r /is4

Tested by
  t4522

    IixVPMACSWW:: PROC
        IiEmitOpcode 0x95
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSWW::

↑ VPMACSWD
  Packed Multiply Accumulate Signed Word to Signed Doubleword
AMD reference

  VPMACSWD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 96 /r /is4

Tested by
  t4522

    IixVPMACSWD:: PROC
        IiEmitOpcode 0x96
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSWD::

↑ VPMACSDQL
  Packed Multiply Accumulate Signed Low Doubleword to Signed Quadword
AMD reference

  VPMACSDQL xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.8 0.xsrc1.0.00 97 /r /is4

Tested by
  t4522

    IixVPMACSDQL:: PROC
        IiEmitOpcode 0x97
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSDQL::

↑ VPMACSDD
  Packed Multiply Accumulate Signed Doubleword to Signed Doubleword
AMD reference

  VPMACSDD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 9E /r /is4

Tested by
  t4522

    IixVPMACSDD:: PROC
        IiEmitOpcode 0x9E
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSDD::

↑ VPMACSDQH
  Packed Multiply Accumulate Signed High Doubleword to Signed Quadword
AMD reference

  VPMACSDQH xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 9F /r /is4

Tested by
  t4522

    IixVPMACSDQH:: PROC
        IiEmitOpcode 0x9F
        JMP IixVPMACSSWW.op:
      ENDP IixVPMACSDQH::

↑ VPMADCSSWD
  Packed Multiply, Add and Accumulate Signed Word to Signed Doubleword with Saturation
AMD reference

  VPMADCSSWD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 A6 /r /is4

Tested by
  t4524

    IixVPMADCSSWD:: PROC
        IiEmitOpcode 0xA6
        JMP IixVPMACSSWW.op:
      ENDP IixVPMADCSSWD::

↑ VPMADCSWD
  Packed Multiply Add and Accumulate Signed Word to Signed Doubleword
AMD reference

  VPMADCSWD xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 B6 /r /is4

Tested by
  t4524

    IixVPMADCSWD:: PROC
        IiEmitOpcode 0xB6
        JMP IixVPMACSSWW.op:
      ENDP IixVPMADCSWD::

↑ VPPERM
  Packed Permute Bytes
AMD reference

  VPPERM xmm1, xmm2, xmm3, xmm4/mem128 | 8F RXB.8 1.xsrc1.0.00 A3 /r is4
  VPPERM xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.8 0.xsrc1.0.00 A3 /r is4

Tested by
  t4524

    IixVPPERM:: PROC
        IiAllowModifier CODE,DATA
        IiRequire AMD, XOP
        IiEmitOpcode 0xA3
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.xmm.mem, xmm.xmm.mem.xmm
    .xmm.xmm.xmm.mem:
        IiEncoding CODE=LONG
        IiSwap Operand3, Operand4
        IiOpEn RVM
        IiIs4 Operand4
        IiEmitPrefix XOP.MAP8.W1.L0
        RET
    .xmm.xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.xmm.mem:
    .xmm.xmm.mem.xmm:
        IiEncoding CODE=SHORT
        IiOpEn RVM
        IiIs4 Operand4
        IiEmitPrefix XOP.MAP8.W0.L0
        RET
      ENDP IixVPPERM::

↑ VPCMOV
  Vector Conditional Moves
AMD reference

  VPCMOV xmm1, xmm2, xmm3/mem128, xmm4 | 8F RXB.08 0.xsrc1.0.00 A2 /r imm[7:4]
  VPCMOV ymm1, ymm2, ymm3/mem256, ymm4 | 8F RXB.08 0.ysrc1.1.00 A2 /r imm[7:4]
  VPCMOV xmm1, xmm2, xmm3, xmm4/mem128 | 8F RXB.08 1.xsrc1.0.00 A2 /r imm[7:4]
  VPCMOV ymm1, ymm2, ymm3, ymm4/mem256 | 8F RXB.08 1.ysrc1.1.00 A2 /r imm[7:4]

Tested by
  t4524

    IixVPCMOV:: PROC
        IiAllowModifier CODE,DATA
        IiRequire AMD, XOP
        IiEmitOpcode 0xA2
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm.xmm, xmm.xmm.mem.xmm, ymm.ymm.ymm.ymm, \
                          ymm.ymm.mem.ymm, xmm.xmm.xmm.mem, ymm.ymm.ymm.mem
    .xmm.xmm.xmm.mem:
        IiEmitPrefix XOP.MAP8.W1.L0
    .L: IiEncoding CODE=LONG
        IiSwap Operand3, Operand4
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.mem:
        IiEmitPrefix XOP.MAP8.W1.L1
        JMP .L:
    .xmm.xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.xmm.mem:
    .xmm.xmm.mem.xmm:
        IiEmitPrefix XOP.MAP8.W0.L0
    .S: IiEncoding CODE=SHORT
        IiOpEn RVM
        IiIs4 Operand4
        RET
    .ymm.ymm.ymm.ymm:
        IiDispatchCode LONG=.ymm.ymm.ymm.mem:
    .ymm.ymm.mem.ymm:
        IiEmitPrefix XOP.MAP8.W0.L1
        JMP .S:
      ENDP IixVPCMOV::

↑ VPROTB
  Packed Rotate Bytes
AMD reference

  VPROTB xmm1, xmm2/mem128, xmm8 | 8F RXB.09 0.xcnt.0.00 90 /r
  VPROTB xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 90 /r
  VPROTB xmm1, xmm2/mem128, imm8 | 8F RXB.08 0.1111.0.00 C0 /r /ib

Tested by
  t4526

    IixVPROTB:: PROC
        MOV CL,0x90
        MOV CH,0xC0
    .op:IiRequire AMD, XOP
        IiAllowModifier CODE,DATA,IMM
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm, xmm.mem.xmm, xmm.xmm.mem, xmm.xmm.imm, xmm.mem.imm
    .xmm.xmm.mem:
        IiEncoding CODE=LONG
        IiEmitOpcode ECX
        IiOpEn RVM
        IiEmitPrefix XOP.MAP9.W1.L0
        RET
    .xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.mem:
    .xmm.mem.xmm:
        IiEncoding CODE=SHORT
        IiEmitOpcode ECX
        IiOpEn RMV
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
    .xmm.xmm.imm:
    .xmm.mem.imm:
        SHR ECX,8
        IiEncoding CODE=SHORT
        IiEmitOpcode ECX
        IiOpEn RM
        IiEmitImm Operand3, BYTE
        IiEmitPrefix XOP.MAP8.W0.L0
        RET
      ENDP IixVPROTB::

↑ VPROTW
  Packed Rotate Words
AMD reference

  VPROTW xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 91 /r
  VPROTW xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 91 /r
  VPROTW xmm1, xmm2/mem128, imm8 | 8F RXB.08 0.1111.0.00 C1 /r /ib

Tested by
  t4526

    IixVPROTW:: PROC
        MOV CL,0x91
        MOV CH,0xC1
        JMP IixVPROTB.op:
      ENDP IixVPROTW::

↑ VPROTD
  Packed Rotate Doublewords
AMD reference

  VPROTD xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 92 /r
  VPROTD xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 92 /r
  VPROTD xmm1, xmm2/mem128, imm8 | 8F RXB.08 0.1111.0.00 C2 /ib

Tested by
  t4526

    IixVPROTD:: PROC
        MOV CL,0x92
        MOV CH,0xC2
        JMP IixVPROTB.op:
      ENDP IixVPROTD::

↑ VPROTQ
  Packed Rotate Quadwords
AMD reference

  VPROTQ xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 93 /r
  VPROTQ xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 93 /r
  VPROTQ xmm1, xmm2/mem128, imm8 | 8F RXB.08 0.1111.0.00 C3 /ib

Tested by
  t4526

    IixVPROTQ:: PROC
        MOV CL,0x93
        MOV CH,0xC3
        JMP IixVPROTB.op:
      ENDP IixVPROTQ::

↑ VPSHLB
  Packed Shift Logical Bytes
AMD reference

  VPSHLB xmm1, xmm2/mem128, xmm3 | 8F RXB.9 0.xcnt.0.00 94 /r
  VPSHLB xmm1, xmm2, xmm3/mem128 | 8F RXB.9 1.xsrc.0.00 94 /r

Tested by
  t4530

    IixVPSHLB:: PROC
        IiEmitOpcode 0x94
    .op:IiRequire AMD, XOP
        IiAllowModifier CODE
        IiModRM /r
        IiDispatchFormat  xmm.xmm.xmm, xmm.mem.xmm, xmm.xmm.mem
    .xmm.xmm.mem:
        IiEncoding CODE=LONG
        IiOpEn RVM
        IiEmitPrefix XOP.MAP9.W1.L0
        RET
    .xmm.xmm.xmm:
        IiDispatchCode LONG=.xmm.xmm.mem:
    .xmm.mem.xmm:
        IiEncoding CODE=SHORT
        IiOpEn RMV
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
      ENDP IixVPSHLB::

↑ VPSHLW
  Packed Shift Logical Words
AMD reference

  VPSHLW xmm1, xmm3/mem128, xmm2 | 8F RXB.09 0.xcnt.0.00 95 /r
  VPSHLW xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 95 /r

Tested by
  t4530

    IixVPSHLW:: PROC
        IiEmitOpcode 0x95
        JMP IixVPSHLB.op:
      ENDP IixVPSHLW::

↑ VPSHLD
  Packed Shift Logical Doublewords
AMD reference

  VPSHLD xmm1, xmm3/mem128, xmm2 | 8F RXB.09 0.xcnt.0.00 96 /r
  VPSHLD xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 96 /r

Tested by
  t4530

    IixVPSHLD:: PROC
        IiEmitOpcode 0x96
        JMP IixVPSHLB.op:
      ENDP IixVPSHLD::

↑ VPSHLQ
  Packed Shift Logical Quadwords
AMD reference

  VPSHLQ xmm1, xmm3/mem128, xmm2 | 8F RXB.09 0.xcnt.0.00 97 /r
  VPSHLQ xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 97 /r

Tested by
  t4530

    IixVPSHLQ:: PROC
        IiEmitOpcode 0x97
        JMP IixVPSHLB.op:
      ENDP IixVPSHLQ::

↑ VPSHAB
  Packed Shift Arithmetic Bytes
AMD reference

  VPSHAB xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 98 /r
  VPSHAB xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 98 /r

Tested by
  t4532

    IixVPSHAB:: PROC
        IiEmitOpcode 0x98
        JMP IixVPSHLB.op:
      ENDP IixVPSHAB::

↑ VPSHAW
  Packed Shift Arithmetic Words
AMD reference

  VPSHAW xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 99 /r
  VPSHAW xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 99 /r

Tested by
  t4532

    IixVPSHAW:: PROC
        IiEmitOpcode 0x99
        JMP IixVPSHLB.op:
      ENDP IixVPSHAW::

↑ VPSHAD
  Packed Shift Arithmetic Doublewords
AMD reference

  VPSHAD xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 9A /r
  VPSHAD xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 9A /r

Tested by
  t4532

    IixVPSHAD:: PROC
        IiEmitOpcode 0x9A
        JMP IixVPSHLB.op:
      ENDP IixVPSHAD::

↑ VPSHAQ
  Packed Shift Arithmetic Quadwords
AMD reference

  VPSHAQ xmm1, xmm2/mem128, xmm3 | 8F RXB.09 0.xcnt.0.00 9B /r
  VPSHAQ xmm1, xmm2, xmm3/mem128 | 8F RXB.09 1.xsrc.0.00 9B /r

Tested by
  t4532

    IixVPSHAQ:: PROC
        IiEmitOpcode 0x9B
        JMP IixVPSHLB.op:
      ENDP IixVPSHAQ::

↑ VFRCZPS
  Extract Fraction Packed Single-Precision Floating-Point
AMD reference

  VFRCZPS xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 80 /r
  VFRCZPS ymm1, ymm2/mem256 | 8F RXB.09 0.1111.1.00 80 /r

Tested by
  t4534

    IixVFRCZPS:: PROC
        IiEmitOpcode 0x80
    .op:IiRequire AMD, XOP
        IiAllowModifier DATA
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat  xmm.xmm, xmm.mem, ymm.ymm, ymm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEncoding DATA=OWORD
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
    .ymm.ymm:
    .ymm.mem:
        IiEncoding DATA=YWORD
        IiEmitPrefix XOP.MAP9.W0.L1
        RET
      ENDP IixVFRCZPS::

↑ VFRCZPD
  xtract Fraction Packed Double-Precision Floating-Point
AMD reference

  VFRCZPD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 81 /r
  VFRCZPD ymm1, ymm2/mem256 | 8F RXB.09 0.1111.1.00 81 /r

Tested by
  t4534

    IixVFRCZPD:: PROC
        IiEmitOpcode 0x81
        JMP IixVFRCZPS.op:
        RET
      ENDP IixVFRCZPD::

↑ VFRCZSS
  Extract Fraction Scalar Single-Precision Floating Point
AMD reference

  VFRCZSS xmm1, xmm2/mem32 | 8F RXB.09 0.1111.0.00 82 /r

Tested by
  t4534

    IixVFRCZSS:: PROC
        IiEmitOpcode 0x82
        IiEncoding DATA=DWORD
    .op:IiRequire AMD, XOP
        IiAllowModifier DATA
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat  xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
      ENDP IixVFRCZSS::

↑ VFRCZSD
  Extract Fraction Scalar Double-Precision Floating-Point
AMD reference

  VFRCZSD xmm1, xmm2/mem64 | 8F RXB.09 0.1111.0.00 83 /r

Tested by
  t4534

    IixVFRCZSD:: PROC
        IiEmitOpcode 0x83
        IiEncoding DATA=QWORD
        JMP IixVFRCZSS.op:
      ENDP IixVFRCZSD::

↑ VPHADDBW
  Packed Horizontal Add Signed Byte to Signed Word
AMD reference

  VPHADDBW xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 C1 /r

Tested by
  t4540

    IixVPHADDBW:: PROC
        IiEmitOpcode 0xC1
    .op:IiRequire AMD, XOP
        IiAllowModifier DATA
        IiOpEn RM
        IiModRM /r
        IiEncoding DATA=OWORD
        IiDispatchFormat  xmm.xmm, xmm.mem
    .xmm.xmm:
    .xmm.mem:
        IiEmitPrefix XOP.MAP9.W0.L0
        RET
      ENDP IixVPHADDBW::

↑ VPHADDBD
  Packed Horizontal Add Signed Byte to Signed Doubleword
AMD reference

  VPHADDBD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 C2 /r

Tested by
  t4540

    IixVPHADDBD:: PROC
        IiEmitOpcode 0xC2
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDBD::

↑ VPHADDBQ
  Packed Horizontal Add Signed Byte to Signed Quadword
AMD reference

  VPHADDBQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 C3 /r

Tested by
  t4540

    IixVPHADDBQ:: PROC
        IiEmitOpcode 0xC3
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDBQ::

↑ VPHADDWD
  Packed Horizontal Add Signed Word to Signed Doubleword
AMD reference

  VPHADDWD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 C6 /r

Tested by
  t4540

    IixVPHADDWD:: PROC
        IiEmitOpcode 0xC6
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDWD::

↑ VPHADDWQ
  Packed Horizontal Add Signed Word to Signed Quadword
AMD reference

  VPHADDWQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 C7 /r

Tested by
  t4540

    IixVPHADDWQ:: PROC
        IiEmitOpcode 0xC7
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDWQ::

↑ VPHADDUBWD
  Packed Horizontal Add Unsigned Byte to Word
AMD reference

  VPHADDUBW xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 D1 /r

Tested by
  t4542

    IixVPHADDUBW:: PROC
        IiEmitOpcode 0xD1
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUBW::

↑ VPHADDUBD
  Packed Horizontal Add Unsigned Byte to Doubleword
AMD reference

  VPHADDUBD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 D2 /r

Tested by
  t4542

    IixVPHADDUBD:: PROC
        IiEmitOpcode 0xD2
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUBD::

↑ VPHADDUBQ
  Packed Horizontal Add Unsigned Byte to Quadword
AMD reference

  VPHADDUBQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 D3 /r

Tested by
  t4542

    IixVPHADDUBQ:: PROC
        IiEmitOpcode 0xD3
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUBQ::

↑ VPHADDUWD
  Packed Horizontal Add Unsigned Word to Doubleword
AMD reference

  VPHADDUWD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 D6 /r

Tested by
  t4542

    IixVPHADDUWD:: PROC
        IiEmitOpcode 0xD6
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUWD::

↑ VPHADDUWQ
  Packed Horizontal Add Unsigned Word to Quadword
AMD reference

  VPHADDUWQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 D7 /r

Tested by
  t4542

    IixVPHADDUWQ:: PROC
        IiEmitOpcode 0xD7
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUWQ::

↑ VPHADDDQ
  Packed Horizontal Add Signed Doubleword to Signed Quadword
AMD reference

  VPHADDDQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 CB /r

Tested by
  t4544

    IixVPHADDDQ:: PROC
        IiEmitOpcode 0xCB
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDDQ::

↑ VPHADDUDQ
  Packed Horizontal Add Unsigned Doubleword to Quadword
AMD reference

  VPHADDUDQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 DB /r

Tested by
  t4544

    IixVPHADDUDQ:: PROC
        IiEmitOpcode 0xDB
        JMP IixVPHADDBW.op:
      ENDP IixVPHADDUDQ::

↑ VPHSUBBW
  Packed Horizontal Subtract Signed Byte to Signed Word
AMD reference

  VPHSUBBW xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 E1 /r

Tested by
  t4544

    IixVPHSUBBW:: PROC
        IiEmitOpcode 0xE1
        JMP IixVPHADDBW.op:
      ENDP IixVPHSUBBW::

↑ VPHSUBWD
  Packed Horizontal Subtract Signed Word to Signed Doubleword
AMD reference

  VPHSUBWD xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 E2 /r

Tested by
  t4544

    IixVPHSUBWD:: PROC
        IiEmitOpcode 0xE2
        JMP IixVPHADDBW.op:
      ENDP IixVPHSUBWD::

↑ VPHSUBDQ
  Packed Horizontal Subtract Signed Doubleword to Signed Quadword
AMD reference

  VPHSUBDQ xmm1, xmm2/mem128 | 8F RXB.09 0.1111.0.00 E3 /r

Tested by
  t4544

    IixVPHSUBDQ:: PROC
        IiEmitOpcode 0xE3
        JMP IixVPHADDBW.op:
      ENDP IixVPHSUBDQ::

↑ VPCOMB
  Compare Vector signed Bytes
AMD reference

  VPCOMB xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 CC /r imm8

Opcode
  CC /r ib
Tested by
  t4550

    IixVPCOMB:: PROC
        MOV CL,0xCC
    .op:IiRequire AMD, XOP, PROT
        IiAllowModifier DATA,IMM
        IiEmitOpcode ECX
        IiOpEn RVM
        IiModRM /r
        IiEmitImm Operand4, BYTE, Max=7
        IiDispatchFormat  xmm.xmm.xmm.imm, xmm.xmm.mem.imm
    .xmm.xmm.xmm.imm:
    .xmm.xmm.mem.imm:
        IiEmitPrefix XOP.MAP8.W0.L0
        RET
      ENDP IixVPCOMB::

↑ VPCOMLTB
  Compare Vector signed Bytes if Less Than
AMD reference

  VPCOMLTB xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 CC /r 00

Opcode
  CC /r 00
Tested by
  t4550

    IixVPCOMLTB:: PROC
        MOV CH,0
        MOV CL,0xCC
    .op:IiRequire AMD, XOP, PROT
        IiAllowModifier DATA,IMM
        MOVB [EDI+II.Operand4+EXP.Low],CH
        MOVB [EDI+II.Operand4+EXP.Status],'N'
        IiEmitOpcode ECX
        IiOpEn RVM
        IiModRM /r
        IiEmitImm Operand4, BYTE
        IiEmitPrefix XOP.MAP8.W0.L0
        IiDispatchFormat  xmm.xmm.xmm, xmm.xmm.mem
    .xmm.xmm.xmm:
    .xmm.xmm.mem:
        RET
      ENDP IixVPCOMLTB::

↑ VPCOMLEB
  Compare Vector signed Bytes if Less than or Equal
AMD reference

  VPCOMLEB xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 CC /r 01

Opcode
  CC /r 01
Tested by
  t4550

    IixVPCOMLEB:: PROC
        MOV CL,0xCC
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEB::

↑ VPCOMGTB
  Compare Vector signed Bytes if Greater Than
AMD reference

  VPCOMGTB xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 CC /r 02

Opcode
  CC /r 02
Tested by
  t4550

    IixVPCOMGTB:: PROC
        MOV CL,0xCC
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTB::

↑ VPCOMGEB
  Compare Vector signed Bytes if Greater than or Equal
AMD reference

  VPCOMGEB xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 CC /r 03

Opcode
  CC /r 03
Tested by
  t4550

    IixVPCOMGEB:: PROC
        MOV CL,0xCC
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEB::

↑ VPCOMEQB
  Compare Vector signed Bytes if EQual
AMD reference

  VPCOMEQB xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 CC /r 04

Opcode
  CC /r 04
Tested by
  t4550

    IixVPCOMEQB:: PROC
        MOV CL,0xCC
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQB::

↑ VPCOMNEQB
  Compare Vector signed Bytes if Not EQual
AMD reference

  VPCOMNEQB xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 CC /r 05

Opcode
  CC /r 05
Tested by
  t4550

    IixVPCOMNEQB:: PROC
        MOV CL,0xCC
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQB::

↑ VPCOMFALSEB
  Compare Vector signed Bytes if FALSE
AMD reference

  VPCOMFALSEB xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 CC /r 06

Opcode
  CC /r 06
Tested by
  t4550

    IixVPCOMFALSEB:: PROC
        MOV CL,0xCC
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEB::

↑ VPCOMTRUEB
  Compare Vector signed Bytes if TRUE
AMD reference

  VPCOMTRUEB xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 CC /r 07

Opcode
  CC /r 07
Tested by
  t4550

    IixVPCOMTRUEB:: PROC
        MOV CL,0xCC
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEB::

↑ VPCOMW
  Compare Vector signed Words
AMD reference

  VPCOMW xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 CD /r imm8

Opcode
  CD /r ib
Tested by
  t4555

    IixVPCOMW:: PROC
        MOV CL,0xCD
        JMP IixVPCOMB.op:
     ENDP IixVPCOMW::

↑ VPCOMLTW
  Compare Vector signed Words if Less Than
AMD reference

  VPCOMLTW xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 CD /r 00

Opcode
  CD /r 00
Tested by
  t4555

    IixVPCOMLTW:: PROC
        MOV CL,0xCD
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTW::

↑ VPCOMLEW
  Compare Vector signed Words if Less than or Equal
AMD reference

  VPCOMLEW xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 CD /r 01

Opcode
  CD /r 01
Tested by
  t4555

    IixVPCOMLEW:: PROC
        MOV CL,0xCD
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEW::

↑ VPCOMGTW
  Compare Vector signed Words if Greater Than
AMD reference

  VPCOMGTW xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 CD /r 02

Opcode
  CD /r 02
Tested by
  t4555

    IixVPCOMGTW:: PROC
        MOV CL,0xCD
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTW::

↑ VPCOMGEW
  Compare Vector signed Words if Greater than or Equal
AMD reference

  VPCOMGEW xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 CD /r 03

Opcode
  CD /r 03
Tested by
  t4555

    IixVPCOMGEW:: PROC
        MOV CL,0xCD
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEW::

↑ VPCOMEQW
  Compare Vector signed Words if EQual
AMD reference

  VPCOMEQW xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 CD /r 04

Opcode
  CD /r 04
Tested by
  t4555

    IixVPCOMEQW:: PROC
        MOV CL,0xCD
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQW::

↑ VPCOMNEQW
  Compare Vector signed Words if Not EQual
AMD reference

  VPCOMNEQW xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 CD /r 05

Opcode
  CD /r 05
Tested by
  t4555

    IixVPCOMNEQW:: PROC
        MOV CL,0xCD
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQW::

↑ VPCOMFALSEW
  Compare Vector signed Words if FALSE
AMD reference

  VPCOMFALSEW xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 CD /r 06

Opcode
  CD /r 06
Tested by
  t4555

    IixVPCOMFALSEW:: PROC
        MOV CL,0xCD
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEW::

↑ VPCOMTRUEW
  Compare Vector signed Words if TRUE
AMD reference

  VPCOMTRUEW xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 CD /r 07

Opcode
  CD /r 07
Tested by
  t4555

    IixVPCOMTRUEW:: PROC
        MOV CL,0xCD
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEW::

↑ VPCOMD
  Compare Vector signed Dwords
AMD reference

  VPCOMD xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 CE /r imm8

Opcode
  CE /r ib
Tested by
  t4560

    IixVPCOMD:: PROC
        MOV CL,0xCE
        JMP IixVPCOMB.op:
     ENDP IixVPCOMD::

↑ VPCOMLTD
  Compare Vector signed Dwords if Less Than
AMD reference

  VPCOMLTD xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 CE /r 00

Opcode
  CE /r 00
Tested by
  t4560

    IixVPCOMLTD:: PROC
        MOV CL,0xCE
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTD::

↑ VPCOMLED
  Compare Vector signed Dwords if Less than or Equal
AMD reference

  VPCOMLED xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 CE /r 01

Opcode
  CE /r 01
Tested by
  t4560

    IixVPCOMLED:: PROC
        MOV CL,0xCE
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLED::

↑ VPCOMGTD
  Compare Vector signed Dwords if Greater Than
AMD reference

  VPCOMGTD xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 CE /r 02

Opcode
  CE /r 02
Tested by
  t4560

    IixVPCOMGTD:: PROC
        MOV CL,0xCE
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTD::

↑ VPCOMGED
  Compare Vector signed Dwords if Greater than or Equal
AMD reference

  VPCOMGED xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 CE /r 03

Opcode
  CE /r 03
Tested by
  t4560

    IixVPCOMGED:: PROC
        MOV CL,0xCE
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGED::

↑ VPCOMEQD
  Compare Vector signed Dwords if EQual
AMD reference

  VPCOMEQD xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 CE /r 04

Opcode
  CE /r 04
Tested by
  t4560

    IixVPCOMEQD:: PROC
        MOV CL,0xCE
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQD::

↑ VPCOMNEQD
  Compare Vector signed Dwords if Not EQual
AMD reference

  VPCOMNEQD xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 CE /r 05

Opcode
  CE /r 05
Tested by
  t4560

    IixVPCOMNEQD:: PROC
        MOV CL,0xCE
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQD::

↑ VPCOMFALSED
  Compare Vector signed Dwords if FALSE
AMD reference

  VPCOMFALSED xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 CE /r 06

Opcode
  CE /r 06
Tested by
  t4560

    IixVPCOMFALSED:: PROC
        MOV CL,0xCE
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSED::

↑ VPCOMTRUED
  Compare Vector signed Dwords if TRUE
AMD reference

  VPCOMTRUED xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 CE /r 07

Opcode
  CE /r 07
Tested by
  t4560

    IixVPCOMTRUED:: PROC
        MOV CL,0xCE
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUED::

↑ VPCOMQ
  Compare Vector signed Qwords
AMD reference

  VPCOMQ xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 CF /r imm8

Opcode
  CF /r ib
Tested by
  t4565

    IixVPCOMQ:: PROC
        MOV CL,0xCF
        JMP IixVPCOMB.op:
     ENDP IixVPCOMQ::

↑ VPCOMLTQ
  Compare Vector signed Qwords if Less Than
AMD reference

  VPCOMLTQ xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 CF /r 00

Opcode
  CF /r 00
Tested by
  t4565

    IixVPCOMLTQ:: PROC
        MOV CL,0xCF
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTQ::

↑ VPCOMLEQ
  Compare Vector signed Qwords if Less than or Equal
AMD reference

  VPCOMLEQ xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 CF /r 01

Opcode
  CF /r 01
Tested by
  t4565

    IixVPCOMLEQ:: PROC
        MOV CL,0xCF
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEQ::

↑ VPCOMGTQ
  Compare Vector signed Qwords if Greater Than
AMD reference

  VPCOMGTQ xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 CF /r 02

Opcode
  CF /r 02
Tested by
  t4565

    IixVPCOMGTQ:: PROC
        MOV CL,0xCF
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTQ::

↑ VPCOMGEQ
  Compare Vector signed Qwords if Greater than or Equal
AMD reference

  VPCOMGEQ xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 CF /r 03

Opcode
  CF /r 03
Tested by
  t4565

    IixVPCOMGEQ:: PROC
        MOV CL,0xCF
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEQ::

↑ VPCOMEQQ
  Compare Vector signed Qwords if EQual
AMD reference

  VPCOMEQQ xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 CF /r 04

Opcode
  CF /r 04
Tested by
  t4565

    IixVPCOMEQQ:: PROC
        MOV CL,0xCF
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQQ::

↑ VPCOMNEQQ
  Compare Vector signed Qwords if Not EQual
AMD reference

  VPCOMNEQQ xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 CF /r 05

Opcode
  CF /r 05
Tested by
  t4565

    IixVPCOMNEQQ:: PROC
        MOV CL,0xCF
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQQ::

↑ VPCOMFALSEQ
  Compare Vector signed Qwords if FALSE
AMD reference

  VPCOMFALSEQ xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 CF /r 06

Opcode
  CF /r 06
Tested by
  t4565

    IixVPCOMFALSEQ:: PROC
        MOV CL,0xCF
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEQ::

↑ VPCOMTRUEQ
  Compare Vector signed Qwords if TRUE
AMD reference

  VPCOMTRUEQ xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 CF /r 07

Opcode
  CF /r 07
Tested by
  t4565

    IixVPCOMTRUEQ:: PROC
        MOV CL,0xCF
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEQ::

↑ VPCOMUB
  Compare Vector Unsigned Bytes
AMD reference

  VPCOMUB xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 EC /r imm8

Opcode
  EC /r ib
Tested by
  t4570

    IixVPCOMUB:: PROC
        MOV CL,0xEC
        JMP IixVPCOMB.op:
     ENDP IixVPCOMUB::

↑ VPCOMLTUB
  Compare Vector Unsigned Bytes if Less Than
AMD reference

  VPCOMLTUB xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 EC /r 00

Opcode
  EC /r 00
Tested by
  t4570

    IixVPCOMLTUB:: PROC
        MOV CL,0xEC
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTUB::

↑ VPCOMLEUB
  Compare Vector Unsigned Bytes if Less than or Equal
AMD reference

  VPCOMLEUB xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 EC /r 01

Opcode
  EC /r 01
Tested by
  t4570

    IixVPCOMLEUB:: PROC
        MOV CL,0xEC
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEUB::

↑ VPCOMGTUB
  Compare Vector Unsigned Bytes if Greater Than
AMD reference

  VPCOMGTUB xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 EC /r 02

Opcode
  EC /r 02
Tested by
  t4570

    IixVPCOMGTUB:: PROC
        MOV CL,0xEC
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTUB::

↑ VPCOMGEUB
  Compare Vector Unsigned Bytes if Greater than or Equal
AMD reference

  VPCOMGEUB xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 EC /r 03

Opcode
  EC /r 03
Tested by
  t4570

    IixVPCOMGEUB:: PROC
        MOV CL,0xEC
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEUB::

↑ VPCOMEQUB
  Compare Vector Unsigned Bytes if EQual
AMD reference

  VPCOMEQUB xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 EC /r 04

Opcode
  EC /r 04
Tested by
  t4570

    IixVPCOMEQUB:: PROC
        MOV CL,0xEC
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQUB::

↑ VPCOMNEQUB
  Compare Vector Unsigned Bytes if Not EQual
AMD reference

  VPCOMNEQUB xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 EC /r 05

Opcode
  EC /r 05
Tested by
  t4570

    IixVPCOMNEQUB:: PROC
        MOV CL,0xEC
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQUB::

↑ VPCOMFALSEUB
  Compare Vector Unsigned Bytes if FALSE
AMD reference

  VPCOMFALSEUB xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 EC /r 06

Opcode
  EC /r 06
Tested by
  t4570

    IixVPCOMFALSEUB:: PROC
        MOV CL,0xEC
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEUB::

↑ VPCOMTRUEUB
  Compare Vector Unsigned Bytes if TRUE
AMD reference

  VPCOMTRUEUB xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 EC /r 07

Opcode
  EC /r 07
Tested by
  t4570

    IixVPCOMTRUEUB:: PROC
        MOV CL,0xEC
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEUB::

↑ VPCOMUW
  Compare Vector Unsigned Words
AMD reference

  VPCOMUW xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 ED /r imm8

Opcode
  ED /r ib
Tested by
  t4575

    IixVPCOMUW:: PROC
        MOV CL,0xED
        JMP IixVPCOMB.op:
     ENDP IixVPCOMUW::

↑ VPCOMLTUW
  Compare Vector Unsigned Words if Less Than
AMD reference

  VPCOMLTUW xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 ED /r 00

Opcode
  ED /r 00
Tested by
  t4575

    IixVPCOMLTUW:: PROC
        MOV CL,0xED
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTUW::

↑ VPCOMLEUW
  Compare Vector Unsigned Words if Less than or Equal
AMD reference

  VPCOMLEUW xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 ED /r 01

Opcode
  ED /r 01
Tested by
  t4575

    IixVPCOMLEUW:: PROC
        MOV CL,0xED
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEUW::

↑ VPCOMGTUW
  Compare Vector Unsigned Words if Greater Than
AMD reference

  VPCOMGTUW xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 ED /r 02

Opcode
  ED /r 02
Tested by
  t4575

    IixVPCOMGTUW:: PROC
        MOV CL,0xED
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTUW::

↑ VPCOMGEUW
  Compare Vector Unsigned Words if Greater than or Equal
AMD reference

  VPCOMGEUW xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 ED /r 03

Opcode
  ED /r 03
Tested by
  t4575

    IixVPCOMGEUW:: PROC
        MOV CL,0xED
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEUW::

↑ VPCOMEQUW
  Compare Vector Unsigned Words if EQual
AMD reference

  VPCOMEQUW xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 ED /r 04

Opcode
  ED /r 04
Tested by
  t4575

    IixVPCOMEQUW:: PROC
        MOV CL,0xED
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQUW::

↑ VPCOMNEQUW
  Compare Vector Unsigned Words if Not EQual
AMD reference

  VPCOMNEQUW xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 ED /r 05

Opcode
  ED /r 05
Tested by
  t4575

    IixVPCOMNEQUW:: PROC
        MOV CL,0xED
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQUW::

↑ VPCOMFALSEUW
  Compare Vector Unsigned Words if FALSE
AMD reference

  VPCOMFALSEUW xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 ED /r 06

Opcode
  ED /r 06
Tested by
  t4575

    IixVPCOMFALSEUW:: PROC
        MOV CL,0xED
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEUW::

↑ VPCOMTRUEUW
  Compare Vector Unsigned Words if TRUE
AMD reference

  VPCOMTRUEUW xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 ED /r 07

Opcode
  ED /r 07
Tested by
  t4575

    IixVPCOMTRUEUW:: PROC
        MOV CL,0xED
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEUW::

↑ VPCOMUD
  Compare Vector Unsigned Dwords
AMD reference

  VPCOMUD xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 EE /r imm8

Opcode
  EE /r ib
Tested by
  t4580

    IixVPCOMUD:: PROC
        MOV CL,0xEE
        JMP IixVPCOMB.op:
     ENDP IixVPCOMUD::

↑ VPCOMLTUD
  Compare Vector Unsigned Dwords if Less Than
AMD reference

  VPCOMLTUD xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 EE /r 00

Opcode
  EE /r 00
Tested by
  t4580

    IixVPCOMLTUD:: PROC
        MOV CL,0xEE
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTUD::

↑ VPCOMLEUD
  Compare Vector Unsigned Dwords if Less than or Equal
AMD reference

  VPCOMLEUD xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 EE /r 01

Opcode
  EE /r 01
Tested by
  t4580

    IixVPCOMLEUD:: PROC
        MOV CL,0xEE
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEUD::

↑ VPCOMGTUD
  Compare Vector Unsigned Dwords if Greater Than
AMD reference

  VPCOMGTUD xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 EE /r 02

Opcode
  EE /r 02
Tested by
  t4580

    IixVPCOMGTUD:: PROC
        MOV CL,0xEE
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTUD::

↑ VPCOMGEUD
  Compare Vector Unsigned Dwords if Greater than or Equal
AMD reference

  VPCOMGEUD xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 EE /r 03

Opcode
  EE /r 03
Tested by
  t4580

    IixVPCOMGEUD:: PROC
        MOV CL,0xEE
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEUD::

↑ VPCOMEQUD
  Compare Vector Unsigned Dwords if EQual
AMD reference

  VPCOMEQUD xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 EE /r 04

Opcode
  EE /r 04
Tested by
  t4580

    IixVPCOMEQUD:: PROC
        MOV CL,0xEE
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQUD::

↑ VPCOMNEQUD
  Compare Vector Unsigned Dwords if Not EQual
AMD reference

  VPCOMNEQUD xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 EE /r 05

Opcode
  EE /r 05
Tested by
  t4580

    IixVPCOMNEQUD:: PROC
        MOV CL,0xEE
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQUD::

↑ VPCOMFALSEUD
  Compare Vector Unsigned Dwords if FALSE
AMD reference

  VPCOMFALSEUD xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 EE /r 06

Opcode
  EE /r 06
Tested by
  t4580

    IixVPCOMFALSEUD:: PROC
        MOV CL,0xEE
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEUD::

↑ VPCOMTRUEUD
  Compare Vector Unsigned Dwords if TRUE
AMD reference

  VPCOMTRUEUD xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 EE /r 07

Opcode
  EE /r 07
Tested by
  t4580

    IixVPCOMTRUEUD:: PROC
        MOV CL,0xEE
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEUD::

↑ VPCOMUQ
  Compare Vector Unsigned Qwords
AMD reference

  VPCOMUQ xmm1, xmm2, xmm3/mem128, imm8 | 8F RXB.8 0.xsrc1.0.00 EF /r imm8

Opcode
  EF /r ib
Tested by
  t4585

    IixVPCOMUQ:: PROC
        MOV CL,0xEF
        JMP IixVPCOMB.op:
     ENDP IixVPCOMUQ::

↑ VPCOMLTUQ
  Compare Vector Unsigned Qwords if Less Than
AMD reference

  VPCOMLTUQ xmm1, xmm2, xmm3/mem128, 0 | 8F RXB.8 0.xsrc1.0.00 EF /r 00

Opcode
  EF /r 00
Tested by
  t4585

    IixVPCOMLTUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x0
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLTUQ::

↑ VPCOMLEUQ
  Compare Vector Unsigned Qwords if Less than or Equal
AMD reference

  VPCOMLEUQ xmm1, xmm2, xmm3/mem128, 1 | 8F RXB.8 0.xsrc1.0.00 EF /r 01

Opcode
  EF /r 01
Tested by
  t4585

    IixVPCOMLEUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x1
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMLEUQ::

↑ VPCOMGTUQ
  Compare Vector Unsigned Qwords if Greater Than
AMD reference

  VPCOMGTUQ xmm1, xmm2, xmm3/mem128, 2 | 8F RXB.8 0.xsrc1.0.00 EF /r 02

Opcode
  EF /r 02
Tested by
  t4585

    IixVPCOMGTUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x2
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGTUQ::

↑ VPCOMGEUQ
  Compare Vector Unsigned Qwords if Greater than or Equal
AMD reference

  VPCOMGEUQ xmm1, xmm2, xmm3/mem128, 3 | 8F RXB.8 0.xsrc1.0.00 EF /r 03

Opcode
  EF /r 03
Tested by
  t4585

    IixVPCOMGEUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x3
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMGEUQ::

↑ VPCOMEQUQ
  Compare Vector Unsigned Qwords if EQual
AMD reference

  VPCOMEQUQ xmm1, xmm2, xmm3/mem128, 4 | 8F RXB.8 0.xsrc1.0.00 EF /r 04

Opcode
  EF /r 04
Tested by
  t4585

    IixVPCOMEQUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x4
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMEQUQ::

↑ VPCOMNEQUQ
  Compare Vector Unsigned Qwords if Not EQual
AMD reference

  VPCOMNEQUQ xmm1, xmm2, xmm3/mem128, 5 | 8F RXB.8 0.xsrc1.0.00 EF /r 05

Opcode
  EF /r 05
Tested by
  t4585

    IixVPCOMNEQUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x5
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMNEQUQ::

↑ VPCOMFALSEUQ
  Compare Vector Unsigned Qwords if FALSE
AMD reference

  VPCOMFALSEUQ xmm1, xmm2, xmm3/mem128, 6 | 8F RXB.8 0.xsrc1.0.00 EF /r 06

Opcode
  EF /r 06
Tested by
  t4585

    IixVPCOMFALSEUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x6
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMFALSEUQ::

↑ VPCOMTRUEUQ
  Compare Vector Unsigned Qwords if TRUE
AMD reference

  VPCOMTRUEUQ xmm1, xmm2, xmm3/mem128, 7 | 8F RXB.8 0.xsrc1.0.00 EF /r 07

Opcode
  EF /r 07
Tested by
  t4585

    IixVPCOMTRUEUQ:: PROC
        MOV CL,0xEF
        MOV CH,0x7
        JMP IixVPCOMLTB.op:
     ENDP IixVPCOMTRUEUQ::

      ENDPROGRAM iix

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