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# iit.htm
Enumerations
IitList
Instruction groups
IitGroupInvalidate
IitGroupPadlock
IitGroupSHA
IitGroupVMX
IitGroupXstate
Instruction handlers
CLGI INVEPT INVLPGA INVPCID INVVPID MONTMUL SHA1MSG1 SHA1MSG2 SHA1NEXTE SHA1RNDS4 SHA256MSG1 SHA256MSG2 SHA256RNDS2 SKINIT STGI VMCALL VMCLEAR VMFUNC VMLAUNCH VMLOAD VMMCALL VMPTRLD VMPTRST VMREAD VMRESUME VMRUN VMSAVE VMWRITE VMXOFF VMXON XABORT XBEGIN XCRYPTCBC XCRYPTCFB XCRYPTCTR XCRYPTECB XCRYPTOFB XEND XGETBV XRSTOR XRSTOR64 XRSTORS XRSTORS64 XSAVE XSAVE64 XSAVEC XSAVEC64 XSAVEOPT XSAVEOPT64 XSAVES XSAVES64 XSETBV XSHA1 XSHA256 XSTORE XTEST

↑ IitHandlers
  assemble TSX, RTM, VMX, SVM extensions of standard instruction set.
See also
  IiHandlers, [RoseCompiler]

    iit PROGRAM FORMAT=COFF,MODEL=FLAT,WIDTH=32
        INCLUDEHEAD euroasm.htm, \  Interface (structures, symbols and macros) of other modules used in this source.
                    ea.htm,eaopt.htm,exp.htm,ii.htm,msg.htm,pgm.htm,pgmopt.htm,sss.htm,stm.htm,sym.htm

    iit HEAD ; Start of module interface.

↑ %IitList
  enumerates machine instructions of this family which €ASM can assemble.
  Each instruction declared in `%IitList` requires the corresponding handler in this file.
See also
  DictLookupIi

    %IitList %SET \
    CLGI, \
    INVEPT, \
    INVLPGA, \
    INVPCID, \
    INVVPID, \
    SKINIT, \
    STGI, \
    VMCALL, \
    VMCLEAR, \
    VMFUNC, \
    VMLAUNCH, \
    VMLOAD, \
    VMMCALL, \
    VMPTRLD, \
    VMPTRST, \
    VMREAD, \
    VMRESUME, \
    VMRUN, \
    VMSAVE, \
    VMWRITE, \
    VMXOFF, \
    VMXON, \
    XABORT, \
    XBEGIN, \
    XEND, \
    XGETBV, \
    XRSTOR, \
    XRSTOR64, \
    XRSTORS, \
    XRSTORS64, \
    XSAVE, \
    XSAVE64, \
    XSAVEC, \
    XSAVEC64, \
    XSAVEOPT, \
    XSAVEOPT64, \
    XSAVES, \
    XSAVES64, \
    XSETBV, \
    XTEST, \
    MONTMUL, \
    XSTORE, \
    XCRYPTECB, \
    XCRYPTCBC, \
    XCRYPTCTR, \
    XCRYPTCFB, \
    XCRYPTOFB, \
    XSHA1, \
    XSHA256, \
    SHA1NEXTE, \
    SHA1MSG1, \
    SHA1MSG2, \
    SHA256MSG1, \
    SHA256MSG2, \
    SHA1RNDS4, \
    SHA256RNDS2, \

    ;

      ENDHEAD iit ; End of module interface.

↑ XBEGIN
  Transactional Begin
Description
  XBEGIN
Category
  RTM
Operands
  rel16/rel32
Opcode
  0xC7F8rel
See also
  IisJMPE.
Tested by
  t4150

    IitXBEGIN:: PROC
        IiRequire 686,TSX
        IiAllowPrefix TsxAny
        IiAllowModifier DIST,DATA,IMM
        IiEmitOpcode 0xC7,0xF8
        JMP IisJMPE.rel::
     ENDP IitXBEGIN::

↑ XTEST
  Test If In Transactional Execution
Description
  XTEST
Category
  RTM
Operands
  -
Opcode
  0x0F01D6
Flags
  ZF
Tested by
  t4150

    IitXTEST:: PROC
        IiRequire 686,TSX
        IiAllowPrefix TsxAny
        IiEmitOpcode 0x0F,0x01,0xD6
        IiDispatchFormat none
    .none:RET
     ENDP IitXTEST::

↑ XABORT
  Transactional Abort
Description
  XABORT
Category
  RTM
Operands
  imm8
Opcode
  0xC6F8 ib
Tested by
  t4150

    IitXABORT:: PROC
        IiRequire 686,TSX
        IiAllowPrefix TsxAny
        IiEmitOpcode 0xC6,0xF8
        IiEmitImm Operand1, BYTE
        IiDispatchFormat imm
    .imm:RET
     ENDP IitXABORT::

↑ XEND
  Transactional End
Description
  XEND
Category
  RTM
Operands
  -
Opcode
  0F 01 D5
Tested by
  t4150

    IitXEND:: PROC
        IiRequire 686,TSX
        IiAllowPrefix TsxAny
        IiEmitOpcode 0x0F,0x01,0xD5
        IiDispatchFormat none
    .none:RET
     ENDP IitXEND::

↑ XGETBV
  Get Value of Extended Control Register specified by ECX into EDX:EAX.
Description
  XGETBV
Category
  system
Operands
  EDX,EAX,ECX,XCR
Opcode
  0x0F01D0
CPU
  C2++
Tested by
  t4155

    IitXGETBV:: PROC
        IiRequire 386
        IiEmitOpcode 0x0F,0x01,0xD0
        IiDispatchFormat none
    .none:RET
     ENDP IitXGETBV::

↑ XSETBV
  Set Extended Control Register specified by ECX from EDX:EAX.
Description
  XSETBV
Category
  system
Operands
  XCR,ECX,EDX,EAX
Opcode
  0x0F01D1
CPU
  C2++
Tested by
  t4155

    IitXSETBV:: PROC
        IiRequire 386,PRIV
        IiEmitOpcode 0x0F,0x01,0xD1
        IiDispatchFormat none
    .none:RET
     ENDP IitXSETBV::

↑ IitGroupXstate
  IitGroupXstate is a common handler for Processor Extended States save/restore instructions.
Input
  ECX has `iiXs64` flag set if 64bit version of instruction is required.
  CL is the opcode second byte 0xAE or 0xC7.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
See also
  XSAVE, XSAVE64, XRSTOR, XRSTOR64, XSAVEOPT, XSAVEOPT64, XRSTORS, XRSTORS64, XSAVEC, XSAVEC64, XSAVES, XSAVES64.
Tested by
  t4155 t4160

    IitGroupXstate:: PROC
        IiRequire 686,SPEC
        IiEmitOpcode 0x0F,ECX
        IiOpEn M
        IiDispatchFormat mem
    .64:IiRequire X64     ; Entry for 64bit Xstate instructions.
        IiEmitPrefix REX.W
        JMP IitGroupXstate:
    .mem:RET
     ENDP IitGroupXstate::

↑ XSAVE
  Save Processor Extended States
Description
  XSAVE
Category
  system
Operands
  mem
Opcode
  0x0FAE /4
CPU
  C2++
Tested by
  t4155

    IitXSAVE:: PROC
        IiModRM /4
        MOV CL,0xAE
        JMP IitGroupXstate:
     ENDP IitXSAVE::

↑ XRSTOR
  Restore Processor Extended States
Description
  XRSTOR
Category
  system
Operands
  mem
Opcode
  0x0FAE /5
CPU
  C2++
Tested by
  t4155

    IitXRSTOR:: PROC
        IiModRM /5
        MOV CL,0xAE
        JMP IitGroupXstate:
     ENDP IitXRSTOR::

↑ XSAVEOPT
  Save Processor Extended States Optimized
Description
  XSAVEOPT
Category
  system
Operands
  mem
Opcode
  0x0FAE /6
Tested by
  t4155

    IitXSAVEOPT:: PROC
        IiModRM /6
        MOV CL,0xAE
        JMP IitGroupXstate:
     ENDP IitXSAVEOPT::

↑ XRSTORS
  Restore Processor Extended States Supervisor
Description
  XRSTORS
Category
  system
Operands
  mem
Opcode
  0x0FC7 /3
Tested by
  t4155

    IitXRSTORS:: PROC
        IiRequire PRIV
        IiModRM /3
        MOV CL,0xC7
        JMP IitGroupXstate:
     ENDP IitXRSTORS::

↑ XSAVEC
  Save Processor Extended States with Compaction
Description
  XSAVEC
Category
  system
Operands
  mem
Opcode
  0x0FC7 /4
Tested by
  t4155

    IitXSAVEC:: PROC
        IiModRM /4
        MOV CL,0xC7
        JMP IitGroupXstate:
     ENDP IitXSAVEC::

↑ XSAVES
  Save Processor Extended States Supervisor
Description
  XSAVES
Category
  system
Operands
  mem
Opcode
  0x0FC7 /5
Tested by
  t4155

    IitXSAVES:: PROC
        IiRequire PRIV
        IiModRM /5
        MOV CL,0xC7
        JMP IitGroupXstate:
     ENDP IitXSAVES::

↑ XSAVE64
  Save Processor Extended64 States
Category
  system
Operands
  mem
Opcode
  0x480FAE /4
CPU
  C2++
Tested by
  t4160

    IitXSAVE64:: PROC
        IiModRM /4
        MOV CL,0xAE
        JMP IitGroupXstate.64:
     ENDP IitXSAVE64::

↑ XRSTOR64
  Restore Processor Extended64 States
Category
  system
Operands
  mem
Opcode
  0x480FAE /5
CPU
  C2++
Tested by
  t4160

    IitXRSTOR64:: PROC
        IiModRM /5
        MOV CL,0xAE
        JMP IitGroupXstate.64:
     ENDP IitXRSTOR64::

↑ XSAVEOPT64
  Save Processor Extended64 States Optimized
Category
  system
Operands
  mem
Opcode
  0x480FAE /6
Tested by
  t4160

    IitXSAVEOPT64:: PROC
        IiModRM /6
        MOV CL,0xAE
        JMP IitGroupXstate.64:
     ENDP IitXSAVEOPT64::

↑ XRSTORS64
  Restore Processor Extended64 States Supervisor
Category
  system
Operands
  mem
Opcode
  0x480FC7 /3
Tested by
  t4160

    IitXRSTORS64:: PROC
        IiRequire PRIV
        IiModRM /3
        MOV CL,0xC7
        JMP IitGroupXstate.64:
     ENDP IitXRSTORS64::

↑ XSAVEC64
  Save Processor Extended64 States with Compaction
Category
  system
Operands
  mem
Opcode
  0x480FC7 /4
Tested by
  t4160

    IitXSAVEC64:: PROC
        IiModRM /4
        MOV CL,0xC7
        JMP IitGroupXstate.64:
     ENDP IitXSAVEC64::

↑ XSAVES64
  Save Processor Extended64 States Supervisor
Category
  system
Operands
  mem
Opcode
  0x480FC7 /5
Tested by
  t4160

    IitXSAVES64:: PROC
        IiRequire PRIV
        IiModRM /5
        MOV CL,0xC7
        JMP IitGroupXstate.64:
     ENDP IitXSAVES64::

↑ IitGroupVMX
  IitGroupVMX is a common handler for operandless VMX (Virtual Machine Extensions) instructions.
Input
  CL is the opcode third byte.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
See also
  VMCALL VMLAUNCH VMRESUME VMXOFF VMFUNC VMRUN VMMCALL VMLOAD VMSAVE STGI CLGI
Tested by
  t4170 t4180

    IitGroupVMX:: PROC
          IiEmitOpcode 0x0F,0x01,ECX
          IiDispatchFormat none
    .none:RET
     ENDP IitGroupVMX::

↑ VMCALL
  Call to VM Monitor
Category
  vmx
Opcode
  0x0F01C1
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4170

    IitVMCALL:: PROC
        IiRequire 686,VMX
        MOV CL,0xC1
        JMP IitGroupVMX:
     ENDP IitVMCALL::

↑ VMLAUNCH
  Launch Virtual Machine
Category
  vmx
Opcode
  0x0F01C2
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4170

    IitVMLAUNCH:: PROC
        IiRequire 686,VMX,PROT
        MOV CL,0xC2
        JMP IitGroupVMX:
     ENDP IitVMLAUNCH::

↑ VMRESUME
  Resume Virtual Machine
Category
  vmx
Opcode
  0x0F01C3
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4170

    IitVMRESUME:: PROC
        IiRequire 686,VMX,PROT
        MOV CL,0xC3
        JMP IitGroupVMX:
     ENDP IitVMRESUME::

↑ VMXOFF
  Leave VMX Operation
Category
  vmx
Opcode
  0x0F01C4
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4170

    IitVMXOFF:: PROC
        IiRequire 686,VMX,PROT
        MOV CL,0xC4
        JMP IitGroupVMX:
     ENDP IitVMXOFF::

↑ VMFUNC
  Invoke VM function
Category
  vmx
Operands
  -
Opcode
  0x0F01D4
Tested by
  t4170

    IitVMFUNC:: PROC
        IiRequire 686,VMX
        MOV CL,0xD4
        JMP IitGroupVMX:
     ENDP IitVMFUNC::

↑ VMRUN
  Run Virtual Machine
Category
  vmx
Operands
  -
Opcode
  0x0F01D8
Tested by
  t4170

    IitVMRUN:: PROC
        IiRequire 686,VMX,AMD,PRIV
        MOV CL,0xD8
        JMP IitGroupVMX:
     ENDP IitVMRUN::

↑ VMMCALL
  Call VMM
Category
  vmx
Operands
  -
Opcode
  0x0F01D9
Tested by
  t4170

    IitVMMCALL:: PROC
        IiRequire 686,VMX,AMD
        MOV CL,0xD9
        JMP IitGroupVMX:
     ENDP IitVMMCALL::

↑ VMLOAD
  Load State from VMCB
Category
  vmx
Operands
  -
Opcode
  0x0F01DA
Tested by
  t4170

    IitVMLOAD:: PROC
        IiRequire 686,VMX,AMD
        MOV CL,0xDA
        JMP IitGroupVMX:
     ENDP IitVMLOAD::

↑ VMSAVE
  Save State to VMCB
Category
  vmx
Operands
  -
Opcode
  0x0F01DB
Tested by
  t4170

    IitVMSAVE:: PROC
        IiRequire 686,VMX,AMD
        MOV CL,0xDB
        JMP IitGroupVMX:
     ENDP IitVMSAVE::

↑ CLGI
  Clear Global Interrupt Flag
Category
  system, AMD, SVM
Operands
  -
Opcode
  0x0F01DD
Tested by
  t4170

    IitCLGI:: PROC
        IiRequire 686,VMX,AMD,PRIV
        MOV CL,0xDD
        JMP IitGroupVMX:
     ENDP IitCLGI::

↑ STGI
  Set Global Interrupt Flag
Category
  vmx
Operands
  -
CPU
  0x0F01DC
Tested by
  t4170

    IitSTGI:: PROC
        IiRequire 686,VMX,AMD,PRIV
        MOV CL,0xDC
        JMP IitGroupVMX:
     ENDP IitSTGI::

↑ VMPTRLD
  Load Pointer to Virtual-Machine Control Structure
Category
  vmx
Operands
  Mq
Opcode
  0x0FC7 /6
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMPTRLD:: PROC
         IiRequire 686,VMX,PRIV,PROT
         IiEmitOpcode 0x0F,0xC7
         IiOpEn M
         IiModRM /6
         IiDispatchFormat mem
    .mem:RET
     ENDP IitVMPTRLD::

↑ VMPTRST
  Store Pointer to Virtual-Machine Control Structure
Category
  vmx
Operands
  Mq
Opcode
  0x0FC7 /7
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMPTRST:: PROC
         IiRequire 686,VMX,PRIV,PROT
         IiEmitOpcode 0x0F,0xC7
         IiOpEn M
         IiModRM /7
         IiDispatchFormat mem
    .mem:RET
        ENDP IitVMPTRST::

↑ VMCLEAR
  Clear Virtual-Machine Control Structure
Category
  vmx
Operands
  Mq
Opcode
  0x660FC7 /6
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMCLEAR:: PROC
     IiRequire 686,VMX,PRIV,PROT
         IiEmitPrefix OTOGGLE
         IiEmitOpcode 0x0F,0xC7
         IiOpEn M
         IiModRM /6
         IiDispatchFormat mem
    .mem:RET
        ENDP IitVMCLEAR::

↑ VMXON
  Enter VMX Operation
Category
  vmx
Operands
  Mq
Opcode
  0xF30FC7 /6
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMXON:: PROC
     IiRequire 686,VMX,PROT
         IiEmitPrefix REPE
         IiEmitOpcode 0x0F,0xC7
         IiOpEn M
         IiModRM /6
         IiDispatchFormat mem
    .mem:RET
        ENDP IitVMXON::

↑ VMREAD
  Read Field from Virtual-Machine Control Structure
Category
  vmx
Operands
  Ed,Gd | Eq,Gq
Opcode
  0x0F78 /r | 0x0F78 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMREAD:: PROC
        IiRequire 686,VMX,PRIV,PROT
        IiEmitOpcode 0x0F,0x78
        IiOpEn MR
        IiModRM /r
        IiDispatchFormat r32.r32,mem.r32,r64.r64,mem.r64
    .r32.r32:
    .mem.r32:IiEncoding DATA=DWORD
         RET
    .r64.r64:
    .mem.r64:IiEncoding DATA=QWORD
        RET
     ENDP IitVMREAD::

↑ VMWRITE
  Write Field to Virtual-Machine Control Structure
Category
  vmx
Operands
  Gd,Ed | Gq,Eq
Opcode
  0x0F79 /r | 0x0F79 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  P4++
Documented
  D42
Tested by
  t4180

    IitVMWRITE:: PROC
        IiRequire 686,VMX,PRIV,PROT
        IiEmitOpcode 0x0F,0x79
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat r32.r32,r32.mem,r64.r64,r64.mem
    .r32.r32:
    .r32.mem:IiEncoding DATA=DWORD
        RET
    .r64.r64:
    .r64.mem:IiEncoding DATA=QWORD
        RET
     ENDP IitVMWRITE::

↑ IitGroupInvalidate
  IitGroupInvalidate is a common handler of invalidating CPU structures instructions with format reg,mem and opcode 0x660F38xx.
Input
  CL is the opcode last byte.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
See also
  INVEPT INVVPID INVPCID
Tested by
  t4190

    IitGroupInvalidate:: PROC
        IiEmitPrefix OTOGGLE
        IiEmitOpcode 0x0F,0x38,ECX
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat r32.mem, r64.mem
    .r64.mem:
        IiAbortIfNot64
        RET
    .r32.mem:
        IiAbortIf64
        RET
     ENDP IitGroupInvalidate::

↑ INVEPT
  Invalidate Translations Derived from EPT
Category
  vmx
Operands
  Gd,Mdq | Gq,Mdq
Opcode
  0x660F3880 /r | 0x660F3880 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  C2++
Documented
  D42
Tested by
  t4190

    IitINVEPT:: PROC
        MOV CL,0x80
        IiRequire VMX,PRIV
        JMP IitGroupInvalidate
     ENDP IitINVEPT::

↑ INVVPID
  Invalidate Translations Based on VPID
Category
  vmx
Operands
  Gd,Mdq | Gq,Mdq
Opcode
  0x660F3881 /r | 0x660F3881 /r
Flags
  modified:O..SZAPC, defined:O..SZAPC
CPU
  C2++
Documented
  D42
Tested by
  t4190

    IitINVVPID:: PROC
        MOV CL,0x81
        IiRequire VMX,PRIV
        JMP IitGroupInvalidate
     ENDP IitINVVPID::

↑ INVPCID
  Invalidate Process-Context Identifier
Description
  INVPCID
Category
  Context
Operands
  reg, mem
Opcode
  0x660F3882 /r
Tested by
  t3403 t4190

    IitINVPCID:: PROC
        MOV CL,0x82
        IiRequire PRIV,SPEC
        JMP IitGroupInvalidate
     ENDP IitINVPCID::

↑ INVLPGA
  Invalidate TLB Entry in a Specified ASID
Operands
  rAX,ECX or none
Opcode
  0x0F01DF
Tested by
  t4190

    IitINVLPGA:: PROC
        IiRequire 686,VMX,AMD,PRIV
        IiEmitOpcode 0x0F,0x01,0xDF
        IiDispatchFormat none,r16.r32,r32.r32,r64.r32
    .67:IiEmitPrefix ATOGGLE
    .none:RET
    .r64.r32:
        IiAbortIfNot64
        IiAbortIfNot Operand1, RAX
        IiAbortIfNot Operand2, ECX
        RET
    .r32.r32:
        IiAbortIf64
        IiAbortIfNot Operand1, EAX
        IiAbortIfNot Operand2, ECX
        IiDispatchWidth BITS16=.67:
        RET
    .r16.r32:
        IiAbortIf64
        IiAbortIfNot Operand1, AX
        IiAbortIfNot Operand2, ECX
        IiDispatchWidth BITS32=.67:
        RET
     ENDP IitINVLPGA::

↑ SKINIT
  Secure Init and Jump with Attestation
Category
  VMX
Operands
  - or EAX
Opcode
  0x0F01DE
Tested by
  t4180

    IitSKINIT:: PROC
        IiRequire 686,VMX,AMD,PRIV,PROT
        IiEncoding DATA=DWORD
        IiEmitOpcode 0x0F,0x01,0xDE
        IiDispatchFormat none,r32
    .r32:IiAbortIfNot Operand1,EAX
    .none:RET
       ENDP IitSKINIT::

↑ IitGroupPadlock
  IitGroupPadlock is a common handler of operandless cryptographic instructions of VIA Nano CPU as specified in Padlock document.
Input
  AL is the opcode 2nd byte.
  CL is the opcode 3rd (last) byte.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
See also
  MONTMUL XCRYPTCBC XCRYPTCFB XCRYPTCTR XCRYPTECB XCRYPTOFB XSHA1 XSHA256 XSTORE
Tested by
  t4110

    IitGroupPadlock:: PROC
        IiRequire 686,CYRIX,SPEC
        IiAllowPrefix REP,ATOGGLE,SEGES
        IiEmitOpcode 0x0F,EAX,ECX
        MOV CH,AL
        CMP CX,0xA7C0 ; XSTORE does not need prefix F3.
        JE .N:
        IiEmitPrefix REP
     .N:IiDispatchFormat none
    .none:RET
     ENDP IitGroupPadlock::

↑ MONTMUL
  Montgomery Multiplier
Category
  crypto
Operands
  -
Opcode
  0xF30FA6C0
Documented
  Padlock
Tested by
  t4110

    IitMONTMUL:: PROC
        MOV AL,0xA6
        MOV CL,0xC0
        JMP IitGroupPadlock:
     ENDP IitMONTMUL::

↑ XSTORE
  Store random bytes
Category
  crypto
Operands
  -
Opcode
  0xF30FA7C0
Documented
  Padlock
Tested by
  t4110

    IitXSTORE:: PROC
        MOV AL,0xA7
        MOV CL,0xC0
        JMP IitGroupPadlock:
     ENDP IitXSTORE::

↑ XCRYPTECB
  Encrypt/decrypt using electronic code book
Category
  crypto
Operands
  -
Opcode
  0xF30FA7C8
Documented
  Padlock
Tested by
  t4110

    IitXCRYPTECB:: PROC
        MOV AL,0xA7
        MOV CL,0xC8
        JMP IitGroupPadlock:
     ENDP IitXCRYPTECB::

↑ XCRYPTCBC
  Encrypt/decrypt using cipher block chaining
Category
  crypto
Operands
  -
Opcode
  0xF30FA7D0
Documented
  Padlock
Tested by
  t4110

    IitXCRYPTCBC:: PROC
        MOV AL,0xA7
        MOV CL,0xD0
        JMP IitGroupPadlock:
     ENDP IitXCRYPTCBC::

↑ XCRYPTCTR
  Encrypt/decrypt using counter mode
Category
  crypto
Operands
  -
Opcode
  0xF30FA7D8
Documented
  Padlock
Tested by
  t4110

    IitXCRYPTCTR:: PROC
        MOV AL,0xA7
        MOV CL,0xD8
        JMP IitGroupPadlock:
     ENDP IitXCRYPTCTR::

↑ XCRYPTCFB
  Encrypt/decrypt using cipher feedback
Category
  crypto
Operands
  -
Opcode
  0xF30FA7E0
Documented
  Padlock
Tested by
  t4110

    IitXCRYPTCFB:: PROC
        MOV AL,0xA7
        MOV CL,0xE0
        JMP IitGroupPadlock:
     ENDP IitXCRYPTCFB::

↑ XCRYPTOFB
  Encrypt/decrypt using output feedback
Category
  crypto
Operands
  -
Opcode
  0xF30FA7E8
Documented
  Padlock
Tested by
  t4110

    IitXCRYPTOFB:: PROC
        MOV AL,0xA7
        MOV CL,0xE8
        JMP IitGroupPadlock:
     ENDP IitXCRYPTOFB::

↑ XSHA1
  Calculate SHA1 as speciﬁed by FIPS 180-2
Category
  crypto
Operands
  -
Opcode
  0xF30FA6C8
Documented
  Padlock
Tested by
  t4110

    IitXSHA1:: PROC
        MOV AL,0xA6
        MOV CL,0xC8
        JMP IitGroupPadlock:
     ENDP IitXSHA1::

↑ XSHA256
  Calculate SHA256 as speciﬁed by FIPS 180-2
Category
  crypto
Operands
  -
Opcode
  0xF30FA6D0
Documented
  Padlock
Tested by
  t4110

    IitXSHA256:: PROC
        MOV AL,0xA6
        MOV CL,0xD0
        JMP IitGroupPadlock:
     ENDP IitXSHA256::

↑ IitGroupSHA
  IitGroupSHA is a common handler of cryptographic instructions with format xmm, xmm/m128.
Input
  CL is the opcode 3rd (last) byte.
  EDI is pointer to II structure with parsed operands.
  EDX has operand types as set by IiAssemble.
See also
  SHA1NEXTE SHA1MSG1 SHA1MSG2 SHA256MSG1 SHA256MSG2

    IitGroupSHA:: PROC
        IiRequire 686,SSE2,SHA
        IiEncoding DATA=OWORD
        IiEmitOpcode 0x0F,0x38,ECX
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat xmm.xmm, xmm.mem
    .xmm.mem:
    .xmm.xmm:
        RET
     ENDP IitGroupSHA::

↑ SHA1NEXTE
  Calculate SHA1 State Variable E after Four Rounds
Tested by
  t4120

    IitSHA1NEXTE:: PROC
        MOV CL,0xC8
        JMP IitGroupSHA:
     ENDP IitSHA1NEXTE::

↑ SHA1MSG1
  Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
Tested by
  t4120

    IitSHA1MSG1:: PROC
        MOV CL,0xC9
        JMP IitGroupSHA:
     ENDP IitSHA1MSG1::

↑ SHA1MSG2
  Perform a Final Calculation for the Next Four SHA1 Message Dwords
Tested by
  t4120

    IitSHA1MSG2:: PROC
        MOV CL,0xCA
        JMP IitGroupSHA:
     ENDP IitSHA1MSG2::

↑ SHA256MSG1
  Perform an Intermediate Calculation for the Next Four SHA256 Message
Tested by
  t4120

    IitSHA256MSG1:: PROC
        MOV CL,0xCC
        JMP IitGroupSHA:
     ENDP IitSHA256MSG1::

↑ SHA256MSG2
  Perform a Final Calculation for the Next Four SHA256 Message Dwords
Tested by
  t4120

    IitSHA256MSG2:: PROC
        MOV CL,0xCD
        JMP IitGroupSHA:
     ENDP IitSHA256MSG2::

↑ SHA1RNDS4
  Perform Four Rounds of SHA1 Operation
Tested by
  t4120

    IitSHA1RNDS4:: PROC
        IiRequire 686,SSE2,SHA
        IiEncoding DATA=OWORD
        IiEmitOpcode 0x0F,0x3A,0xCC
        IiOpEn RM
        IiModRM /r
        IiEmitImm Operand3, BYTE
        IiDispatchFormat xmm.xmm.imm, xmm.mem.imm
    .xmm.mem.imm:
    .xmm.xmm.imm:
        RET
     ENDP IitSHA1RNDS4::

↑ SHA256RNDS2
  Perform Two Rounds of SHA256 Operation
Tested by
  t4120

    IitSHA256RNDS2:: PROC
        IiRequire 686,SSE2,SHA
        IiEncoding DATA=OWORD
        IiEmitOpcode 0x0F,0x38,0xCB
        IiOpEn RM
        IiModRM /r
        IiDispatchFormat xmm.xmm, xmm.mem, xmm.xmm.xmm, xmm.mem.xmm
    .xmm.xmm.xmm:
    .xmm.mem.xmm:
        IiAbortIfNot Operand3,XMM0
    .xmm.mem:
    .xmm.xmm:
        RET
     ENDP IitSHA256RNDS2::

      ENDPROGRAM iit

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