| Index | Manual | Download | Source | Macros | Embedded word Case ins.
Sitemap | Links | Forum | Tests | Projects

# Test t5415: Machine instructions VFMADD312PD VFMADD123PD VFMADD321PD VFMSUB312PD VFMSUB123PD VFMSUB321PD

Tested procedures
  IibVFMADD312PD IibVFMADD123PD IibVFMADD321PD IibVFMSUB312PD IibVFMSUB123PD IibVFMSUB321PD

Source & expected listing t5415.htm.lst
  `| | EUROASM LIST=ON,DUMP=ON,DUMPWIDTH=34,DUMPALL=OFF,CPU=X64,SIMD=AVX512,FMA=ON,EVEX=ON, MVEX=ON | |t5415 PROGRAM FORMAT=BIN, LISTMAP=OFF, LISTGLOBALS=OFF |[Mode64] |[Mode64] SEGMENT WIDTH=64,PURPOSE=CODE |00000000:C4E2E998CB | VFMADD312PD XMM1,XMM2,XMM3 |00000005:C4E2E9984D40 | VFMADD312PD XMM1,XMM2,[RBP+40h] |0000000B:62F2ED0C984D04<4 | VFMADD312PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000012:62F2ED18984D08<3 | VFMADD312PD XMM1,XMM2,[RBP+40h],BCST=ON |00000019:C4E2ED98CB | VFMADD312PD YMM1,YMM2,YMM3 |0000001E:C4E2ED984D40 | VFMADD312PD YMM1,YMM2,[RBP+40h] |00000024:62F2EDAC984D02<5 | VFMADD312PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000002B:62F2ED38984D08<3 | VFMADD312PD YMM1,YMM2,[RBP+40h],BCST=ON |00000032:62F2ED4898CB | VFMADD312PD ZMM1,ZMM2,ZMM3 |00000038:62F2ED7898CB | VFMADD312PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000003E:62F2E91C98CB | VFMADD312PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000044:62F2E99C98CB | VFMADD312PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000004A:62F2ED48984D01<6 | VFMADD312PD ZMM1,ZMM2,[RBP+40h] |00000051:62F2EDCC984D01<6 | VFMADD312PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000058:62F2ED58984D08<3 | VFMADD312PD ZMM1,ZMM2,[RBP+40h],BCST=ON |0000005F:62F2E908984D01<6 | VFMADD312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |00000066:62F2E918984D08<3 | VFMADD312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |0000006D:62F2E928984D02<5 | VFMADD312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |00000074:C4E2E9A8CB | VFMADD123PD XMM1,XMM2,XMM3 |00000079:C4E2E9A84D40 | VFMADD123PD XMM1,XMM2,[RBP+40h] |0000007F:62F2ED0CA84D04<4 | VFMADD123PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000086:62F2ED18A84D08<3 | VFMADD123PD XMM1,XMM2,[RBP+40h],BCST=ON |0000008D:C4E2EDA8CB | VFMADD123PD YMM1,YMM2,YMM3 |00000092:C4E2EDA84D40 | VFMADD123PD YMM1,YMM2,[RBP+40h] |00000098:62F2EDACA84D02<5 | VFMADD123PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000009F:62F2ED38A84D08<3 | VFMADD123PD YMM1,YMM2,[RBP+40h],BCST=ON |000000A6:62F2ED48A8CB | VFMADD123PD ZMM1,ZMM2,ZMM3 |000000AC:62F2ED78A8CB | VFMADD123PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |000000B2:62F2E91CA8CB | VFMADD123PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |000000B8:62F2E99CA8CB | VFMADD123PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |000000BE:62F2ED48A84D01<6 | VFMADD123PD ZMM1,ZMM2,[RBP+40h] |000000C5:62F2EDCCA84D01<6 | VFMADD123PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |000000CC:62F2ED58A84D08<3 | VFMADD123PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000000D3:62F2E908A84D01<6 | VFMADD123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000000DA:62F2E918A84D08<3 | VFMADD123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000000E1:62F2E928A84D02<5 | VFMADD123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |000000E8:C4E2E9B8CB | VFMADD321PD XMM1,XMM2,XMM3 |000000ED:C4E2E9B84D40 | VFMADD321PD XMM1,XMM2,[RBP+40h] |000000F3:62F2ED0CB84D04<4 | VFMADD321PD XMM1,XMM2,[RBP+40h],MASK=K4 |000000FA:62F2ED18B84D08<3 | VFMADD321PD XMM1,XMM2,[RBP+40h],BCST=ON |00000101:C4E2EDB8CB | VFMADD321PD YMM1,YMM2,YMM3 |00000106:C4E2EDB84D40 | VFMADD321PD YMM1,YMM2,[RBP+40h] |0000010C:62F2EDACB84D02<5 | VFMADD321PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000113:62F2ED38B84D08<3 | VFMADD321PD YMM1,YMM2,[RBP+40h],BCST=ON |0000011A:62F2ED48B8CB | VFMADD321PD ZMM1,ZMM2,ZMM3 |00000120:62F2ED78B8CB | VFMADD321PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |00000126:62F2E91CB8CB | VFMADD321PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |0000012C:62F2E99CB8CB | VFMADD321PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |00000132:62F2ED48B84D01<6 | VFMADD321PD ZMM1,ZMM2,[RBP+40h] |00000139:62F2EDCCB84D01<6 | VFMADD321PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000140:62F2ED58B84D08<3 | VFMADD321PD ZMM1,ZMM2,[RBP+40h],BCST=ON |00000147:62F2E908B84D01<6 | VFMADD321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |0000014E:62F2E918B84D08<3 | VFMADD321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |00000155:62F2E928B84D02<5 | VFMADD321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |0000015C:C4E2E99ACB | VFMSUB312PD XMM1,XMM2,XMM3 |00000161:C4E2E99A4D40 | VFMSUB312PD XMM1,XMM2,[RBP+40h] |00000167:62F2ED0C9A4D04<4 | VFMSUB312PD XMM1,XMM2,[RBP+40h],MASK=K4 |0000016E:62F2ED189A4D08<3 | VFMSUB312PD XMM1,XMM2,[RBP+40h],BCST=ON |00000175:C4E2ED9ACB | VFMSUB312PD YMM1,YMM2,YMM3 |0000017A:C4E2ED9A4D40 | VFMSUB312PD YMM1,YMM2,[RBP+40h] |00000180:62F2EDAC9A4D02<5 | VFMSUB312PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000187:62F2ED389A4D08<3 | VFMSUB312PD YMM1,YMM2,[RBP+40h],BCST=ON |0000018E:62F2ED489ACB | VFMSUB312PD ZMM1,ZMM2,ZMM3 |00000194:62F2ED789ACB | VFMSUB312PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000019A:62F2E91C9ACB | VFMSUB312PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |000001A0:62F2E99C9ACB | VFMSUB312PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |000001A6:62F2ED489A4D01<6 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h] |000001AD:62F2EDCC9A4D01<6 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |000001B4:62F2ED589A4D08<3 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000001BB:62F2E9089A4D01<6 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000001C2:62F2E9189A4D08<3 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000001C9:62F2E9289A4D02<5 | VFMSUB312PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |000001D0:C4E2E9AACB | VFMSUB123PD XMM1,XMM2,XMM3 |000001D5:C4E2E9AA4D40 | VFMSUB123PD XMM1,XMM2,[RBP+40h] |000001DB:62F2ED0CAA4D04<4 | VFMSUB123PD XMM1,XMM2,[RBP+40h],MASK=K4 |000001E2:62F2ED18AA4D08<3 | VFMSUB123PD XMM1,XMM2,[RBP+40h],BCST=ON |000001E9:C4E2EDAACB | VFMSUB123PD YMM1,YMM2,YMM3 |000001EE:C4E2EDAA4D40 | VFMSUB123PD YMM1,YMM2,[RBP+40h] |000001F4:62F2EDACAA4D02<5 | VFMSUB123PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |000001FB:62F2ED38AA4D08<3 | VFMSUB123PD YMM1,YMM2,[RBP+40h],BCST=ON |00000202:62F2ED48AACB | VFMSUB123PD ZMM1,ZMM2,ZMM3 |00000208:62F2ED78AACB | VFMSUB123PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |0000020E:62F2E91CAACB | VFMSUB123PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000214:62F2E99CAACB | VFMSUB123PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000021A:62F2ED48AA4D01<6 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h] |00000221:62F2EDCCAA4D01<6 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |00000228:62F2ED58AA4D08<3 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h],BCST=ON |0000022F:62F2E908AA4D01<6 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |00000236:62F2E918AA4D08<3 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |0000023D:62F2E928AA4D02<5 | VFMSUB123PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. |00000244:C4E2E9BACB | VFMSUB321PD XMM1,XMM2,XMM3 |00000249:C4E2E9BA4D40 | VFMSUB321PD XMM1,XMM2,[RBP+40h] |0000024F:62F2ED0CBA4D04<4 | VFMSUB321PD XMM1,XMM2,[RBP+40h],MASK=K4 |00000256:62F2ED18BA4D08<3 | VFMSUB321PD XMM1,XMM2,[RBP+40h],BCST=ON |0000025D:C4E2EDBACB | VFMSUB321PD YMM1,YMM2,YMM3 |00000262:C4E2EDBA4D40 | VFMSUB321PD YMM1,YMM2,[RBP+40h] |00000268:62F2EDACBA4D02<5 | VFMSUB321PD YMM1,YMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000026F:62F2ED38BA4D08<3 | VFMSUB321PD YMM1,YMM2,[RBP+40h],BCST=ON |00000276:62F2ED48BACB | VFMSUB321PD ZMM1,ZMM2,ZMM3 |0000027C:62F2ED78BACB | VFMSUB321PD ZMM1,ZMM2,ZMM3,ROUND=ZERO |00000282:62F2E91CBACB | VFMSUB321PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=0,OPER=1 ; Swap inner pairs {cdab}. |00000288:62F2E99CBACB | VFMSUB321PD ZMM1,ZMM2,ZMM3,MASK=K4,EH=1,OPER=1 ; Round down. |0000028E:62F2ED48BA4D01<6 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h] |00000295:62F2EDCCBA4D01<6 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h],MASK=K4,ZEROING=ON |0000029C:62F2ED58BA4D08<3 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h],BCST=ON |000002A3:62F2E908BA4D01<6 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=0 ; {8to8}. |000002AA:62F2E918BA4D08<3 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=1 ; {1to8}. |000002B1:62F2E928BA4D02<5 | VFMSUB321PD ZMM1,ZMM2,[RBP+40h],PREFIX=MVEX,OPER=2 ; {4to8}. | |ENDPROGRAM t5415`

Expected messages t5415.out
  `I0180 Assembling source file "t5415.htm". I0270 Assembling source "t5415". I0310 Assembling source pass 1. I0330 Assembling source pass 2 - final. I0470 Assembling program "t5415". "t5415.htm"{64} I0510 Assembling program pass 1. "t5415.htm"{64} I0530 Assembling program pass 2 - final. "t5415.htm"{64} I0660 16bit TINY BIN file "t5415.bin" created, size=696. "t5415.htm"{174} I0650 Program "t5415" assembled in 2 passes with errorlevel 0. "t5415.htm"{174} I0750 Source "t5415" (192 lines) assembled in 2 passes with errorlevel 0. I0860 Listing file "t5415.htm.lst" created, size=9003. I0990 EuroAssembler terminated with errorlevel 0.`

▲Back to the top▲